Altera Stratix V Avalon-ST Manuel d'utilisateur Page 34
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Parameter Value Description
Endpoint L1
acceptable
latency
Maximum of 1 us
Maximum of 2 us
Maximum of 4 us
Maximum of 8 us
Maximum of 16 us
Maximum of 32 us
No limit
This value indicates the acceptable latency that an Endpoint
can withstand in the transition from the L1 to L0 state. It is an
indirect measure of the Endpoint’s internal buffering. It sets
the read-only value of the Endpoint L1 acceptable latency field
of the Device Capabilities Register.
This Endpoint does not support the L0s or L1 states. However,
a switched system may include links connected to switches
that have L0s and L1 enabled. This parameter is set to allow
system configuration software to read the acceptable latencies
for all devices in the system and the exit latencies for each link
to determine which links can enable Active State Power
Management (ASPM). This setting is disabled for Root Ports.
The default value of this parameter is 1 µs. This is the safest
setting for most designs.
PHY Characteristics
Table 3-10: PHY Characteristics
Parameter Value Description
Gen2 transmit
deemphasis
3.5dB
6dB
Specifies the transmit de-emphasis for Gen2. Altera
recommends the following settings:
• 3.5dB: Short PCB traces
• 6.0dB: Long PCB traces.
Use ATX PLL On/Off When enabled, the Hard IP for PCI Express uses the ATX PLL
instead of the CMU PLL Using the ATX PLL instead of the
CMU PLL reduces the number of transceiver channels that are
necessary for Gen1 and Gen2 variants. This option requires
the use of the soft reset controller and does not support the
CvP flow. For more information about channel placement,
refer to Serial Data Signals on page 4-30.
Enable Common
Clock Configura‐
tion (for lower
latency)
On/Off When you turn this option on, the Application Layer and
Transaction Layer use a common clock. Using a common
clock reduces datapath latency because synchronizers are not
necessary.
This parameter is only available for the Avalon-ST interface.
3-14
PHY Characteristics
UG-01097_sriov
2014.12.15
Altera Corporation
Parameter Settings
Send Feedback
- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Example Designs 8
- Debug Features 8
- IP Core Verification 9
- Recommended Speed Grades 10
- Related Information 11
- Subscribe 12
- Qsys Subsystem Description 13
- Parameter Value 15
- Directory Description 16
- Parameter Settings 21
- Parameter Value Description 22
- SR-IOV System Settings 24
- Interrupt Capabilities 27
- Device Capabilities 29
- Error Reporting 30
- Link Capabilities 31
- Slot Capabilities 32
- Power Management 33
- PHY Characteristics 34
- Simulation Options 35
- Avalon-ST TX Interface 37
- Signal Direction Description 38
- Avalon‑ST RX Interface 40
- BAR Hit Signals 43
- Completion Side Band Signals 45
- Signal Directi 46
- Description 46
- Clock Signals 48
- Interrupt Interface 49
- Implementing MSI-X Interrupts 55
- LMI Signals 57
- Serial Data Signals 65
- Test Signals 70
- PIPE Interface Signals 71
- Byte Address 77
- MSI Registers 80
- MSI-X Capability Structure 82
- VF Device ID Register 96
- Page Size Registers 96
- Lane Error Status Register 98
- Bits Register Description 99
- Default Value 99
- Altera Corporation 100
- Registers 100
- Send Feedback 100
- Virtual Function Registers 102
- Name Description 103
- Reset and Clocks 107
- Hard IP for PCI Express 108
- Example Design 108
- UG-01097_sriov 109
- 2014.12.15 109
- Function Level Reset (FLR) 111
- Clock Domains 111
- Clock Summary 114
- Interrupts 115
- Error Handling 118
- Physical Layer Errors 119
- Data Link Layer Errors 119
- Transaction Layer Errors 120
- Error Type Description 121
- Status Bit Conditions 123
- IP Core Architecture 125
- Top-Level Interfaces 126
- Clocks and Reset 126
- Transceiver Reconfiguration 126
- Data Link Layer 127
- Physical Layer 129
- TX Packets 130
- Design Implementation 136
- CONF_DONE 137
- Endpoint Reset 137
- Root Port Reset 137
- SDC Timing Constraints 138
- Debugging 143
- Setting Up Simulation 146
- Use Third-Party PCIe Analyzer 148
- BIOS Enumeration Issues 148
- Address[31:2] 149
- Figure A-6: I/O Read Request 151
- Additional Information 155
- Typographic Conventions 156
- Visual Cue Meaning 157
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