Altera Stratix V Advanced Systems Development Board Manuel d'utilisateur télécharger pdf (Page 71)

Chapter 2: Board Components 2–61

Memory

January 2014 Altera Corporation Stratix V Advanced Systems Development Board

Reference Manual

B21

MOSYS2_CMDARX_P0

1.4-V PCML AG4 Transceiver output

D20

MOSYS2_CMDARX_P1

1.4-V PCML AE4 Transceiver output

B19

MOSYS2_CMDARX_P2

1.4-V PCML AC4 Transceiver output

D18

MOSYS2_CMDARX_P3

1.4-V PCML AA4 Transceiver output

B17

MOSYS2_CMDARX_P4

1.4-V PCML W4 Transceiver output

D16

MOSYS2_CMDARX_P5

1.4-V PCML U4 Transceiver output

B15

MOSYS2_CMDARX_P6

1.4-V PCML R4 Transceiver output

D14

MOSYS2_CMDARX_P7

1.4-V PCML N4 Transceiver output

A11

MOSYS2_CMDBRX_N0

1.4-V PCML L3 Transceiver output

C10

MOSYS2_CMDBRX_N1

1.4-V PCML J3 Transceiver output

MOSYS2_CMDBRX_N2

1.4-V PCML K5 Transceiver output

MOSYS2_CMDBRX_N3

1.4-V PCML H5 Transceiver output

MOSYS2_CMDBRX_N4

1.4-V PCML G3 Transceiver output

MOSYS2_CMDBRX_N5

1.4-V PCML F5 Transceiver output

MOSYS2_CMDBRX_N6

1.4-V PCML E3 Transceiver output

MOSYS2_CMDBRX_N7

1.4-V PCML D5 Transceiver output

B11

MOSYS2_CMDBRX_P0

1.4-V PCML L4 Transceiver output

D10

MOSYS2_CMDBRX_P1

1.4-V PCML J4 Transceiver output

MOSYS2_CMDBRX_P2

1.4-V PCML K6 Transceiver output

MOSYS2_CMDBRX_P3

1.4-V PCML H6 Transceiver output

MOSYS2_CMDBRX_P4

1.4-V PCML G4 Transceiver output

MOSYS2_CMDBRX_P5

1.4-V PCML F6 Transceiver output

MOSYS2_CMDBRX_P6

1.4-V PCML E4 Transceiver output

MOSYS2_CMDBRX_P7

1.4-V PCML D6 Transceiver output

T22

MOSYS2_CONFIGN

1.5-V CMOS A16 Configuration enable

H22

MOSYS2_DMON_N0

1.5-V CMOS — Digital monitor

MOSYS2_DMON_N1

1.5-V CMOS — Digital monitor

G22

MOSYS2_DMON_P0

1.5-V CMOS — Digital monitor

MOSYS2_DMON_P1

1.5-V CMOS — Digital monitor

K22

MOSYS2_EVENTAN

1.5-V CMOS C16 Error detect (CMDARX)

L21

MOSYS2_EVENTBN

1.5-V CMOS H15 Error detect (CMDBRX)

AB21

MOSYS2_QATX_N0

1.4-V PCML AK1 Transceiver input

Y20

MOSYS2_QATX_N1

1.4-V PCML AH1 Transceiver input

AB19

MOSYS2_QATX_N2

1.4-V PCML AF1 Transceiver input

Y18

MOSYS2_QATX_N3

1.4-V PCML AD1 Transceiver input

AB17

MOSYS2_QATX_N4

1.4-V PCML AB1 Transceiver input

Y16

MOSYS2_QATX_N5

1.4-V PCML Y1 Transceiver input

AB15

MOSYS2_QATX_N6

1.4-V PCML V1 Transceiver input

Y14

MOSYS2_QATX_N7

1.4-V PCML T1 Transceiver input

Table 2–27. MoSys MSR576 Interface Pin Assignments, Signal Names and Functions (Part 4 of 5)

Board Reference Schematic Signal Name I/O Standard

Stratix V GX FPGA

Device Pin Number

Description

1 2 ... 66 67 68 69 70 71 72 73 74 75 76 ... 83 84

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Altera Stratix V Advanced Systems Development Board Manuel d'utilisateur Page 71

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