Altera Stratix V Advanced Systems Development Board Manuel d'utilisateur télécharger pdf (Page 58)

2–48 Chapter 2: Board Components

Memory

Stratix V Advanced Systems Development Board January 2014 Altera Corporation

Reference Manual

Table 2–23 lists the DDR3 devices pin assignments, signal names, and functions for

FPGA2.

DQS_N7

Differential 1.5-V

SSTL Class I

BD28 D15 Data strobe

ODT

1.5-V SSTL Class I AE31 R18 On-die termination enable

RASN

1.5-V SSTL Class I AF31 G17 Row address strobe

RESETN

1.5-V SSTL Class I AE34 A19 Reset

WEN

1.5-V SSTL Class I AP33 F17 Write enable

ZQ01

— — — ZQ impedance calibration

ZQ02

— — — ZQ impedance calibration

ZQ03

— — — ZQ impedance calibration

ZQ04

— — — ZQ impedance calibration

Table 2–23. FPGA1 DDR3 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 7 of 7)

Board

Reference

Schematic

Signal Name

I/O Standard Stratix V GX FPGA1 Device Pin Number Description

Table 2–24. FPGA2 DDR3 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 6)

Board

Reference

Schematic

Signal Name

I/O Standard Stratix V GX FPGA2 Device Pin Number Description

DDR3E_

DDR3G_

(x32 bit interface) DDR3E DDR3G

1.5-V SSTL Class I AW20 G28 Address bus

1.5-V SSTL Class I AT21 G26 Address bus

1.5-V SSTL Class I BD20 F26 Address bus

1.5-V SSTL Class I BB20 D29 Address bus

1.5-V SSTL Class I AU20 A26 Address bus

1.5-V SSTL Class I BC20 C27 Address bus

1.5-V SSTL Class I AU21 C28 Address bus

1.5-V SSTL Class I BA22 B28 Address bus

1.5-V SSTL Class I BD22 A28 Address bus

1.5-V SSTL Class I BB21 E27 Address bus

A10

1.5-V SSTL Class I AY21 H27 Address bus

A11

1.5-V SSTL Class I AW21 F28 Address bus

A12

1.5-V SSTL Class I AV20 H28 Address bus

A13

1.5-V SSTL Class I BC22 D27 Address bus

BA0

1.5-V SSTL Class I AU22 F29 Bank address bus

BA1

1.5-V SSTL Class I AT20 B26 Bank address bus

BA2

1.5-V SSTL Class I BA21 T27 Bank address bus

CASN

1.5-V SSTL Class I AR21 K28 Column address strobe

CKE

1.5-V SSTL Class I AP21 G29 Clock enable

CLK_N

Differential 1.5-V

SSTL Class I

AW22 H26 Differential output clock

1 2 ... 53 54 55 56 57 58 59 60 61 62 63 ... 83 84

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Altera Stratix V Advanced Systems Development Board Manuel d'utilisateur Page 58

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