
2–44 Chapter 2: Board Components
Memory
Stratix V Advanced Systems Development Board January 2014 Altera Corporation
Reference Manual
H3
DQ20
1.5-V SSTL Class I BD26 J25 Data bus
H8
DQ21
1.5-V SSTL Class I AY25 J24 Data bus
G2
DQ22
1.5-V SSTL Class I BA24 G25 Data bus
H7
DQ23
1.5-V SSTL Class I BC26 H23 Data bus
D7
DQ24
1.5-V SSTL Class I AL23 N23 Data bus
C3
DQ25
1.5-V SSTL Class I AK23 L23 Data bus
C8
DQ26
1.5-V SSTL Class I AL24 T23 Data bus
C2
DQ27
1.5-V SSTL Class I AK21 K24 Data bus
A7
DQ28
1.5-V SSTL Class I AM23 U24 Data bus
A2
DQ29
1.5-V SSTL Class I AJ22 L24 Data bus
B8
DQ30
1.5-V SSTL Class I AN23 T24 Data bus
A3
DQ31
1.5-V SSTL Class I AJ23 M23 Data bus
F3
DQS_P0
Differential 1.5-V
SSTL Class I
BC25 C25 Data strobe
G3
DQS_N0
Differential 1.5-V
SSTL Class I
BD25 C24 Data strobe
C7
DQS_P1
Differential 1.5-V
SSTL Class I
AG21 L27 Data strobe
B7
DQS_N1
Differential 1.5-V
SSTL Class I
AH21 K27 Data strobe
F3
DQS_P2
Differential 1.5-V
SSTL Class I
BA25 K26 Data strobe
G3
DQS_N2
Differential 1.5-V
SSTL Class I
BB26 K25 Data strobe
C7
DQS_P3
Differential 1.5-V
SSTL Class I
AR23 R24 Data strobe
B7
DQS_N3
Differential 1.5-V
SSTL Class I
AT23 P24 Data strobe
K1
ODT
1.5-V SSTL Class I AR20 G29 On-die termination enable
J3
RASN
1.5-V SSTL Class I AR21 D29 Row address strobe
T2
RESETN
1.5-V SSTL Class I AR24 H28 Reset
L3
WEN
1.5-V SSTL Class I BB20 C28 Write enable
L8
ZQ01
— — — ZQ impedance calibration
L8
ZQ02
— — — ZQ impedance calibration
DDR3B_
/
DDR3D_
(x64 bit interface) DDR3B DDR3D
N3
A0
1.5-V SSTL Class I AJ32 J19 Address bus
P7
A1
1.5-V SSTL Class I AM32 E17 Address bus
P3
A2
1.5-V SSTL Class I AR31 K18 Address bus
N2
A3
1.5-V SSTL Class I AG33 L18 Address bus
P8
A4
1.5-V SSTL Class I AE29 D18 Address bus
Table 2–23. FPGA1 DDR3 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 7)
Board
Reference
Schematic
Signal Name
I/O Standard Stratix V GX FPGA1 Device Pin Number Description
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