Altera Stratix V Advanced Systems Development Board Manuel d'utilisateur télécharger pdf (Page 55)

Chapter 2: Board Components 2–45

Memory

January 2014 Altera Corporation Stratix V Advanced Systems Development Board

Reference Manual

1.5-V SSTL Class I AE33 M18 Address bus

1.5-V SSTL Class I AJ33 B17 Address bus

1.5-V SSTL Class I AF34 B19 Address bus

1.5-V SSTL Class I AD33 H19 Address bus

1.5-V SSTL Class I AN31 C18 Address bus

A10

1.5-V SSTL Class I AR32 N17 Address bus

A11

1.5-V SSTL Class I AP31 E18 Address bus

A12

1.5-V SSTL Class I AN33 M17 Address bus

A13

1.5-V SSTL Class I AM31 A17 Address bus

BA0

1.5-V SSTL Class I AH33 K17 Bank address bus

BA1

1.5-V SSTL Class I AK33 L17 Bank address bus

BA2

1.5-V SSTL Class I AK32 H17 Bank address bus

CASN

1.5-V SSTL Class I AE30 P17 Column address strobe

CKE

1.5-V SSTL Class I AG32 H16 Clock enable

CLK_N

Differential 1.5-V

SSTL Class I

AE32 P18 Differential output clock

CLK_P

Differential 1.5-V

SSTL Class I

AD32 P19 Differential output clock

CSN

1.5-V SSTL Class I AF32 R19 Chip select

DM0

1.5-V SSTL Class I BC31 F22 Data write mask

DM1

1.5-V SSTL Class I AK24 L21 Data write mask

DM2

1.5-V SSTL Class I AN30 V19 Data write mask

DM3

1.5-V SSTL Class I AG29 W18 Data write mask

DM4

1.5-V SSTL Class I AV29 H14 Data write mask

DM5

1.5-V SSTL Class I AV32 P16 Data write mask

DM6

1.5-V SSTL Class I AV26 U15 Data write mask

DM7

1.5-V SSTL Class I BA27 C13 Data write mask

DQ0

1.5-V SSTL Class I AW30 A20 Data bus

DQ1

1.5-V SSTL Class I BB30 C21 Data bus

DQ2

1.5-V SSTL Class I BD31 B20 Data bus

DQ3

1.5-V SSTL Class I BC32 E20 Data bus

DQ4

1.5-V SSTL Class I BB32 B22 Data bus

DQ5

1.5-V SSTL Class I AY31 F21 Data bus

DQ6

1.5-V SSTL Class I BD32 A22 Data bus

DQ7

1.5-V SSTL Class I BA30 E21 Data bus

DQ8

1.5-V SSTL Class I AH24 F20 Data bus

DQ9

1.5-V SSTL Class I AJ24 J21 Data bus

DQ10

1.5-V SSTL Class I AH28 G20 Data bus

DQ11

1.5-V SSTL Class I AK26 J22 Data bus

Table 2–23. FPGA1 DDR3 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 7)

Board

Reference

Schematic

Signal Name

I/O Standard Stratix V GX FPGA1 Device Pin Number Description

1 2 ... 50 51 52 53 54 55 56 57 58 59 60 ... 83 84

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Altera Stratix V Advanced Systems Development Board Manuel d'utilisateur Page 55

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