Altera Stratix V Advanced Systems Development Board Manuel d'utilisateur télécharger pdf (Page 31)

Chapter 2: Board Components 2–21

Configuration, Status, and Setup Elements

January 2014 Altera Corporation Stratix V Advanced Systems Development Board

Reference Manual

MAX V Reset Push Button

The MAX V reset push button,

MAX_RESETn

(S3) is an input to the MAX V CPLD

System Controller. This push button is the default reset for the CPLD logic.

Program Load Push Button

The program load push button,

PGM_CONFIG

(S2) is an input to the MAX V CPLD

System Controller. The push button forces a reconfiguration of the FPGA from flash

memory. The location in the flash memory is based on the settings of the

PGM_LED[2:0]

which is controlled by the program select push button,

PGM_SEL

(S1).

Program Select Push Button

The program select push button,

PGM_SEL

(S1) is an input to the MAX V CPLD System

Controller. The push button toggles the

PGM_LED[2:0]

setting that selects which

location in the flash memory is used to configure the FPGA. Refer to Table 2–7 for the

configuration settings.

CPU Reset Push Buttons

The CPU reset push buttons,

FPGA1_CPU_RESETn

(S7) and

FPGA2_CPU_RESETn

(S11) are

inputs to the

DEV_CLRn

pins of the Stratix V GX FPGA1 and FPGA2 devices

respectively, and are open-drain I/O pins from the MAX V CPLD System Controller.

These push buttons are the default reset for the FPGA logic. The MAX V System

Controller also drives this push button during POR.

You must enable the

CPU_RESETn

signal within the Quartus II software for this reset

function to work. Otherwise, the

FPGA1_CPU_RESETn

and

FPGA2_CPU_RESETn

act as

regular I/O pins. When you enable the signal and then pull the signal high on the

board, these push buttons reset every register within the FPGA with a low signal.

PCIE_PRSNT2n_x8

ON: Enable x8 presence detect

OFF: Disable x8 presence detect

PCIE_PRSNT2n_x16

ON: Enable x16 presence detect

OFF: Disable x16 presence detect

Table 2–11. PCI Express Control DIP Switch Controls (Part 2 of 2)

Switch (SW8) Schematic Signal Name Description

1 2 ... 26 27 28 29 30 31 32 33 34 35 36 ... 83 84

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Altera Stratix V Advanced Systems Development Board Manuel d'utilisateur Page 31

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