Altera Stratix V Advanced Systems Development Board Manuel d'utilisateur télécharger pdf (Page 45)

Chapter 2: Board Components 2–35

Components and Interfaces

January 2014 Altera Corporation Stratix V Advanced Systems Development Board

Reference Manual

B16

FMC_DP_M2C_P6

1.4-V PCML H43 Transceiver receive channel

B12

FMC_DP_M2C_P7

1.4-V PCML F43 Transceiver receive channel

FMC_DP_M2C_P8

1.4-V PCML D43 Transceiver receive channel

FMC_DP_M2C_P9

1.4-V PCML C41 Transceiver receive channel

C34

FMC_GA0

2.5-V CMOS BD7 Geographic address 0, I

C channel select

D35

FMC_GA1

2.5-V CMOS BC7 Geographic address 1, I

C channel select

FMC_GBTCLK_M2C_P0

LVDS

AB39 Transceiver reference clock

FMC_GBTCLK_M2C_N0

AB40 Transceiver reference clock

B20

FMC_GBTCLK_M2C_P1

LVDS

V39 Transceiver reference clock

B21

FMC_GBTCLK_M2C_N1

V40 Transceiver reference clock

D29

JTAG_TCK

2.5-V CMOS AL34 JTAG clock

D34

FMC_JTAG_RST

2.5-V CMOS — JTAG reset

D30

FMC_JTAG_TDI

2.5-V CMOS — JTAG mode select

D31

FMC_JTAG_TDO

2.5-V CMOS — JTAG data out

D33

FMC_JTAG_TMS

2.5-V CMOS — JTAG data in

FMC_LA_RX_CLK_P0

LVDS

(adjustable

VCCIO)

M8 LVDS or CMOS clock input

FMC_LA_RX_CLK_N0

L8 LVDS or CMOS clock input

FMC_LA_RX_CLK_P1

LVDS

(adjustable

VCCIO)

B8 LVDS or CMOS clock input

FMC_LA_RX_CLK_N1

A8 LVDS or CMOS clock input

G10

FMC_LA_RX_N0

LVDS

(adjustable

VCCIO, 2.5 V

default)

H10 LVDS receive or single-ended data bus

C11

FMC_LA_RX_N1

T11 LVDS receive or single-ended data bus

G13

FMC_LA_RX_N2

H8 LVDS receive or single-ended data bus

C15

FMC_LA_RX_N3

V9 LVDS receive or single-ended data bus

G16

FMC_LA_RX_N4

F10 LVDS receive or single-ended data bus

C19

FMC_LA_RX_N5

V11 LVDS receive or single-ended data bus

G19

FMC_LA_RX_N6

F8 LVDS receive or single-ended data bus

C23

FMC_LA_RX_N7

N13 LVDS receive or single-ended data bus

G22

FMC_LA_RX_N8

D9 LVDS receive or single-ended data bus

G25

FMC_LA_RX_N9

C12 LVDS receive or single-ended data bus

G28

FMC_LA_RX_N10

A11 LVDS receive or single-ended data bus

C27

FMC_LA_RX_N11

N14 LVDS receive or single-ended data bus

G31

FMC_LA_RX_N12

F11 LVDS receive or single-ended data bus

G34

FMC_LA_RX_N13

L11 LVDS receive or single-ended data bus

G37

FMC_LA_RX_N14

T9 LVDS receive or single-ended data bus

Table 2–21. FMC Port Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 5)

Board

Reference

(J8)

Schematic Signal

Name

I/O Standard

Stratix V GX FPGA1

Device Pin Number

Description

1 2 ... 40 41 42 43 44 45 46 47 48 49 50 ... 83 84

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Altera Stratix V Advanced Systems Development Board Manuel d'utilisateur Page 45

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