Altera Hybrid Memory Cube Controller Manuel d'utilisateur télécharger pdf (Page 7)

• 128-byte READ response (9-FLIT packet)

• MODE READ response (2-FLIT packet)

• MODE WRITE response (single FLIT packet)

The HMC Controller IP core does not process other packet types. Reception of any other packet type

might cause the IP core to fail.

Device Family Support

The following table lists the device support level definitions for Altera IP cores.

Table 1-1: Altera IP Core Device Support Levels

FPGA Device Families

Preliminary support — The core is verified with preliminary timing models for this device family. The IP

core meets all functional requirements, but might still be undergoing timing analysis for the device family. It

can be used in production designs with caution.

Final support — The IP core is verified with final timing models for this device family. The IP core meets all

functional and timing requirements for the device family and can be used in production designs.

The following table shows the level of support offered by the HMC Controller IP core for each Altera

device family.

Table 1-2: HMC Controller IP Core Device Family Support

Device Family Support

Arria 10 Preliminary

All other device families No support

IP Core Verification

Before releasing a version of the HMC Controller IP core, Altera runs comprehensive regression tests in

the current version of the Quartus

II software. The HMC Controller IP Core is tested in simulation and

hardware to confirm functionality.

Related Information

Knowledge Base Errata for HMC Controller IP core

Exceptions to functional correctness are documented in the HMC Controller IP core errata.

Altera IP Release Notes

Changes to the HMC Controller IP core are noted in the Altera IP Release Notes starting from the

Quartus II software v15.0.

1-4

Device Family Support

UG-01152

2015.05.04

Altera Corporation

About the Altera Hybrid Memory Cube Controller IP Core

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Altera Hybrid Memory Cube Controller Manuel d'utilisateur Page 7