Altera Arria V Avalon-ST Manuel d'utilisateur

Arria V Avalon-ST Interface for PCIe SolutionsUser GuideLast updated for Altera Complete Design Suite: 14.1 Subscribe

Figure 1-5: Example Design Preset Parameters• Targeted Device Family• Lanes• Lane Rate• Application Clock Rate• Port type• Application Interface• Tags

Type 0 Configuration Space RegistersFigure 5-1: Type 0 Configuration Space Registers - Byte Address Offsets and LayoutEndpoints store configuration da

Type 1 Configuration Space RegistersFigure 5-2: Type 1 Configuration Space Registers (Root Ports)0x00000x004Device ID31242316158700x0080x00C0x0100x014

Figure 5-4: MSI-X Capability Structure0x0680x06C0x070Message Control Next Cap PtrMSI-X Table OffsetMSI-X Pending Bit Array (PBA) Offset31 24 23 16 15

Figure 5-7: PCI Express Capability Structure - Byte Address Offsets and LayoutIn the following table showing the PCI Express Capability Structure, reg

Altera-Defined VSEC RegistersFigure 5-8: VSEC RegistersThis extended capability structure supports Configuration via Protocol (CvP) programming and de

Table 5-3: Altera‑Defined Vendor Specific HeaderYou can specify these values when you instantiate the Hard IP. These registers are read-only at run-ti

Table 5-7: CvP StatusThe CvP Status register allows software to monitor the CvP status signals.Bits Register Description Reset Value Access[31:26] Res

Bits Register Description Reset Value Access[1] HIP_CLK_SEL. Selects between PMA and fabric clock when USER_MODE = 1 and PLD_CORE_READY = 1. The follo

Bits Register Description Reset Value Access[1] START_XFER. Sets the CvP output to the FPGA control blockindicating the start of a transfer.1’b0 RW[0]

Bits Register Description Reset Value Access[0] Mask for the RX buffer uncorrectable ECC error. 1b’1 RWSUncorrectable Internal Error Status RegisterTa

Related InformationDebugging on page 17-1IP Core VerificationTo ensure compliance with the PCI Express specification, Altera performs extensive verifi

Bits Register DescriptionResetValueAccess[1] When set, indicates a retry buffer uncorrectable ECC error.0RW1CS[0] When set, indicates a RX buffer unco

Bits Register Description Reset Value Access[4:2] Reserved. 0 RO[1] When set, the retry buffer correctable ECC error status indicatesan error.0 RW1CS[

Reset and Clocks62014.12.15SubscribeSend FeedbackThe pin_perst signal from the input pin of the FPGA resets the Hard IP for PCI Express IP Core.app_rs

Figure 6-1: Reset Controller Block DiagramExample Designaltpcie_dev_hip_<if>_hwtcl.valtpcied_<dev>_hwtcl.svTransceiver HardReset Logic/Sof

Reset Sequence for Hard IP for PCI Express IP Core and Application LayerFigure 6-2: Hard IP for PCI Express and Application Logic Reset SequenceYour A

Figure 6-3: RX Transceiver Reset Sequencebusy_xcvr_reconfigrx_pll_lockedrx_analogresetltssmstate[4:0]txdetectrx_loopbackpipe_phystatuspipe_rxstatus[2:

For descriptions of the available reset signals, refer to Reset Signals, Status, and Link Training Signals.Related InformationHard IP Status on page 4

As this figure indicates, the IP core includes the following clock domains:pclkThe transceiver derives pclk from the 100 MHz refclk signal that you mu

Link Width Maximum Link Rate Avalon Interface Width coreclkout_hip×8 Gen1128125 MHz×1Gen2 64125 MHz×2Gen2 64125 MHz×4 Gen2 128 125 MHzpld_clkcoreclkou

Interrupts72014.12.15SubscribeSend FeedbackInterrupts for EndpointsThe Arria V Hard IP for PCI Express provides support for PCI Express MSI, MSI-X, an

Table 1-5: Arria V Recommended Speed Grades for Link Widths and Application Layer Clock FrequenciesAltera recommends setting the Quartus II Analysis &

Figure 7-1: MSI Handler BlockMSI HandlerBlockapp_msi_reqapp_msi_ackapp_msi_tc[2:0]app_msi_num[4:0]app_msi_func[2:0]app_int_sts_vec[7:0]cfg_msicsr[15:0

There are 32 possible MSI messages. The number of messages requested by a particular component doesnot necessarily correspond to the number of message

be deasserted before or within the same clock as app_msi_ack is deasserted to avoid inferring a newinterrupt.Figure 7-4: MSI Interrupt Signals Timingc

Figure 7-5: MSI-X Interrupt ComponentsHostRXTXRXTXMSI-XPCIe with Avalon-ST I/FMSI-X TableIRQProcessorMSI-X PBAIRQ SourceApplication LayerHost SW Prog

Figure 7-7: MSI-X PBA TablePending Bits 0 through 63Pending Bits 64 through 127Pending Bits ((N - 1) div 64) × 64 through N - 1QWORD 0QWORD 1QWORD ((

Related InformationCorrespondence between Configuration Space Registers and the PCIe Specification on page 5-1Enabling MSI or Legacy InterruptsThe PCI

Error Handling82014.12.15SubscribeSend FeedbackEach PCI Express compliant device must implement a basic level of error management and can optionallyim

Physical Layer ErrorsTable 8-2: Errors Detected by the Physical LayerThe following table describes errors detected by the Physical Layer. Physical Lay

Transaction Layer ErrorsTable 8-4: Errors Detected by the Transaction LayerError Type DescriptionPoisoned TLP received Uncorrectable(non-fatal)This er

Error Type DescriptionIn all cases the TLP is deleted in the Hard IP block andnot presented to the Application Layer. If the TLP is anon-posted reques

supports ModelSim®-Altera for all IP. The PCIe cores support the Aldec RivieraPro, Cadence NCsim,Mentor Graphics ModelSim, and Synopsys VCS and VCS-MX

Error Type DescriptionUnexpected completion Uncorrectable(non-fatal)This error is caused by an unexpected completiontransaction. The Hard IP block han

Error Type DescriptionMalformed TLP Uncorrectable(fatal)This error is caused by any of the following conditions:• The data payload of a received TLP e

Poisoned TLPs can also set the parity error bits in the PCI Configuration Space Status register.Table 8-5: Parity Error ConditionsStatus Bit Condition

Figure 8-2: Correctable Error Status RegisterThe default value of all the bits of this register is 0. An error status bit that is set indicates that t

IP Core Architecture92014.12.15SubscribeSend FeedbackThe Arria V Hard IP for PCI Express implements the complete PCI Express protocol stack as defined

Figure 9-1: Arria V Hard IP for PCI Express Using the Avalon-ST InterfaceClockDomainCrossing(CDC)Data LinkLayer(DLL)Transaction Layer (TL)PHYMAC Hard

Related InformationPCI Express Base Specification 2.1 or 3.0Top-Level InterfacesAvalon-ST InterfaceAn Avalon-ST interface connects the Application Lay

Local Management Interface (LMI Interface)The LMI bus provides access to the PCI Express Configuration Space in the Transaction Layer.Related Informat

Transaction LayerThe Transaction Layer is located between the Application Layer and the Data Link Layer. It generates andreceives Transaction Layer Pa

Figure 9-2: Architecture of the Transaction Layer: Dedicated Receive BufferTransaction Layer TX DatapathTransaction Layer RX DatapathAvalon-STRX Contr

Getting Started with the Arria V Hard IP for PCIExpress22014.12.15SubscribeSend FeedbackThis section provides instructions to help you quickly customi

The Configuration Space also generates all messages (PME#, INT, error, slot power limit), MSI requests,and completion packets from configuration reque

Figure 9-3: Data Link LayerTo Transaction LayerTx Transaction LayerPacket Description & DataTransaction LayerPacket GeneratorRetry BufferTo Physic

• ACK/NAK Packets—The ACK/NAK block handles ACK/NAK DLLPs and generates the sequencenumber of transmitted packets.• Transaction Layer Packet Checker—T

Figure 9-4: Physical Layer ArchitectureScrambler8B10BEncoderLane nTX+ / TX-Scrambler8B10BEncoderLane 0TX+ / TX-Descrambler8B10BDecoderLane nRX+ / RX-E

The PHYMAC block comprises four main sub-blocks:• MAC Lane—Both the RX and the TX path use this block.• On the RX side, the block decodes the Physical

PCI Express Base Specification 2.1. Examples of settings that require arbitration include the followingfeatures:• Link Control settings• Error detecti

Transaction Layer Protocol (TLP) Details102014.12.15SubscribeSend FeedbackSupported Message TypesINTX MessagesThe following table describes the messag

MessageRootPortEndpointGenerated byCommentsAppLayerCore Core(withAppLayerinput)Deassert_INTBReceive Transmit No No NoDeassert_INTCReceive Transmit No

Error Signaling MessagesTable 10-3: Error Signaling MessagesMessageRootPortEndpointGenerated byCommentsAppLayerCore Core (withApp Layerinput)ERR_CORRX

Locked Transaction MessageTable 10-4: Locked Transaction MessageMessage Root Port EndpointGenerated byCommentsAppLayerCore Core (withApp Layerinput)Un

For a detailed explanation of this example design, refer to the Testbench and Design Example chapter. Ifyou choose the parameters specified in this ch

Message Root Port EndpointGenerated byCommentsAppLayerCore Core (withApp Layerinput)VendorDefinedType 1TransmitReceiveTransmitReceiveYes No NoHot Plug

Message Root Port EndpointGenerated byCommentsAppLayerCore Core (withApp Layerinput)AttentionButton_Pressed(Endpoint only)Receive Transmit No No YesN/

• The Type 0 Configuration TLPs are only routed to the Configuration Space of the Hard IP and are notsent downstream on the PCI Express link.• The Typ

• A Memory Write or Message Request with the Relaxed Ordering Attribute bit clear (b’0) must not passany other Memory Write or Message Request.• A Mem

Can the Row Passthe Column?Posted Req Non Posted ReqCompletionMemory Write orMessage ReqRead Request I/O or Cfg Write ReqCmplCmpl NoY/NNoNoYes Yes Yes

Figure 10-1: Design Including Legacy PCI Buses Requiring Strong OrderingProducerPCI-toPCI BridgePCI BusFlagPostedWrite BufferConsumerPCI BusMemoryRead

Figure 10-2: PCI Express Design Using Relaxed OrderingRootComplexPCIeEndpointSwitchWrite BufferFullCPUMemoryPCIe Bridge to PCI or PCI-XLegacyEndpointP

Throughput Optimization112014.12.15SubscribeSend FeedbackThe PCI Express Base Specification defines a flow control mechanism to ensure efficient trans

Figure 11-1: Flow Control Update LoopCreditsConsumedCounterCreditLimitData PacketFlowControlGatingLogic(CreditCheck)AllowIncrRxBufferData PacketCredit

counter. Essentially, this means the data sink knows the data source has less than a fullMAX_PAYLOAD worth of credits, and therefore is starving.b. Wh

Figure 2-2: Complete Gen1 ×4 Endpoint (DUT) Connected to Example Design (APPS)The example design includes the following components:• DUT—This is Gen1

Nevertheless, maintaining maximum throughput of completion data packets is important. Endpointsmust offer an infinite number of completion credits. En

Design Implementation122014.12.15SubscribeSend FeedbackCompleting your design includes additional steps to specify analog properties, pin assignments,

You can also enter these commands at the Quartus II Tcl Console. For example, the following commandsets the XCVR_VCCR_VCCT_VOLTAGE to 1.0 V for the pi

Optional Features132014.12.15SubscribeSend FeedbackConfiguration via Protocol (CvP)The Hard IP for PCI Express architecture has an option to configure

CvP has the following advantages:• Provides a simpler software model for configuration. A smart host can use the PCIe protocol and theapplication topo

Table 13-2: ECRC Operation on RX PathECRC Forwarding ECRC Check Enable(6)ECRC Status Error TLP Forward to Application LayerNoNonone No Forwardedgood N

Table 13-3: ECRC Generation and Forwarding on TX PathAll unspecified cases are unsupported and the behavior of the Hard IP is unknown.ECRC Forwarding

Hard IP Reconfiguration142014.12.15SubscribeSend FeedbackThe Arria V Hard IP for PCI Express reconfiguration block allows you to dynamically change th

Transceiver PHY IP Reconfiguration152014.12.15SubscribeSend FeedbackAs silicon progresses towards smaller process nodes, circuit performance is affect

As this figure illustrates, the reconfig_to_xcvr[ <n> 70-1:0] and reconfig_from_xcvr[ <n> 46-1:0]buses connect the two components. You mus

Generating the TestbenchFollow these steps to generate the chaining DMA testbench:1. On the Generate menu, select Generate Testbench System. Specify t

number of logical interfaces by merging them. Allowing the Quartus II software to merge reconfi‐guration interfaces gives the Fitter more flexibility

Testbench and Design Example162014.12.15SubscribeSend FeedbackThis chapter introduces the Root Port or Endpoint design example including a testbench,

Your Application Layer design may need to handle at least the following scenarios that are not possible tocreate with the Altera testbench and the Roo

The top-level of the testbench instantiates four main modules:• <qsys_systemname>— This is the example Endpoint design. For more information abo

Root Port TestbenchThis testbench simulates up to an ×8 PCI Express link using either the PIPE interfaces of the Root Portand Endpoints or the serial

The end point or Root Port variant is generated in the language (Verilog HDL or VHDL) that you selectedfor the variation file. The testbench files are

Figure 16-2: Top-Level Chaining DMA Example for SimulationRoot Complex CPURoot Port MemoryWriteDescriptorTableDataChaining DMAEndpoint MemoryAvalon-M

The following modules are included in the design example and located in the subdirectory<qsys_systemname>/testbench/<qsys_system_name>_tb/

The following modules are provided in both Verilog HDL:• altpcierd_example_app_chaining—This top level module contains the logic related to the Avalon

• altpcierd_read_dma_requester, altpcierd_read_dma_requester_128—For each descriptor located inthe altpcierd_descriptor FIFO, this module transfers da

Generating Quartus II Synthesis Files1. On the Generate menu, select Generate HDL.2. For Create HDL design files for synthesis, select Verilog.You can

Memory BAR MappingExpansion ROM BAR Not implemented by design example; behavior is unpredictable.I/O Space BAR (any) Not implemented by design example

Table 16-3: Bit Definitions for the Control Field in the DMA Write Control Register and DMA Read ControlRegisterBit Field Description16 Reserved —17MS

Addr Register NameBits[31:24] Bits[23:16] Bits[15:0]0x24DMA Wr Status LoTarget Mem AddressWidthWrite DMA Performance Counter. (Clockcycles from time D

Bit Field Description[15:0]Write DMA EPLASIndicates the number of the last descriptor completed by the writeDMA. For simultaneous DMA read and write t

Each subsequent descriptor consists of a minimum of four dwords of data and corresponds to one DMAtransfer. (A dword equals 32 bits.)Note: The chainin

The following table shows the layout of the descriptor fields following the descriptor header.Table 16-8: Chaining DMA Descriptor Format MapBits[31:22

Descriptor Field EndpointAccessRC Access DescriptionEPLAST_ENAR R/W This bit is OR’d with the EPLAST_ENA bit of the controlregister. When EPLAST_ENA i

• The chaining DMA writes the EPLast bit of the Chaining DMA Descriptor Tableaftercompleting the data transfer for the first and last descriptors.• Th

Table 16-12: Write Descriptor 1Offset in BFMShared MemoryValue DescriptionDW0 0x820 1,024 Transfer length in dwords and control bits as described inBi

Table 16-14: DMA Control Register Setup for DMA WriteOffset in DMAControl Register(BAR2)Value DescriptionDW0 0x0 3 Number of descriptors and control b

Complete the following steps to create your Quartus II project:1. Click the New Project Wizard icon.2. Click Next in the New Project Wizard: Introduct

Table 16-16: Read Descriptor 1Offset in BFMShared MemoryValue DescriptionDW0 0x920 1,024 Transfer length in dwords and control bits as described in on

Offset in DMA ControlRegisters (BAR2)Value DescriptionDW1 0x14 0 BFM shared memoryupper address valueDW2 0x18 0x900 BFM shared memorylower address val

Figure 16-3: Root Port Design Example Root Port Variation(variation_name.v)Avalon-ST Interface(altpcietb_bfm_vc_intf)Test Driver(altpcietb_bfm_driver_

The top-level of the testbench instantiates the following key files:• altlpcietb_bfm_top_ep.v— this is the Endpoint BFM. This file also instantiates t

Figure 16-4: Root Port BFMBFM Shared Memory(altpcietb_bfm_shmem _common)BFM Log Interface(altpcietb_bfm_log_common)Root Port RTL Model (altpcietb_bfm_

• BFM Read/Write Request Functions(altpcietb_bfm_driver_rp.v)—These functions provide the basicBFM calls for PCI Express read and write requests. For

The ebfm_cfg_rp_ep executes the following steps to initialize the Configuration Space:1. Sets the Root Port Configuration Space to enable the Root Por

configuration is unlikely to be useful in real systems. If the procedure is unable to assign the BARs,it displays an error message and stops the simul

Offset (Bytes) Description+60 ReservedThe configuration routine does not configure any advanced PCI Express capabilities such as the AERcapability.Bes

Figure 16-6: Memory Space Layout—No Limit Root Complex Shared MemoryUnusedUnusedConfiguration ScratchSpace Used byRoutines - NotWriteable by UserCal

Datasheet12014.12.15SubscribeSend FeedbackArria V Avalon-ST Interface for PCIe DatasheetAltera® Arria® V FPGAs include a configurable, hardened protoc

# PHY IP reconfig controller constraints# Set reconfig_xcvr clock# Modify to match the actual clock pin name# used for this clock, and also changed to

Figure 16-7: I/O Address Space Root Complex Shared MemoryUnusedConfiguration ScratchSpace Used by BFMRoutines - NotWriteable by UserCalls or EndpointB

Verilog HDL include file altpcietb_bfm_driver_rp.v. The complete list of available procedures andfunctions is as follows:• ebfm_barwr—writes data from

Location altpcietb_bfm_rdwr.vArgumentsbar_tableAddress of the Endpoint bar_table structure in BFM sharedmemory. The bar_table structure stores the add

Location altpcietb_bfm_driver_rp.vArgumentsbar_tableAddress of the Endpoint bar_table structure in BFM sharedmemory. The bar_table structure stores th

Argumentsbar_tableAddress of the Endpoint bar_table structure in BFM sharedmemory. The bar_table structure stores the address assigned toeach BAR so t

ebfm_cfgwr_imm_wait ProcedureThe ebfm_cfgwr_imm_wait procedure writes up to four bytes of data to the specified configurationregister. This procedure

Location altpcietb_bfm_driver_rp.vSyntax ebfm_cfgwr_imm_nowt(bus_num, dev_num, fnc_num, imm_regb_adr, regb_len, imm_data)Argumentsbus_numPCI Express b

Location altpcietb_bfm_driver_rp.vArgumentsbus_numPCI Express bus number of the target device.dev_numPCI Express device number of the target device.fn

Location altpcietb_bfm_driver_rp.vArgumentsbus_numPCI Express bus number of the target device.dev_numPCI Express device number of the target device.fn

Location altpcietb_bfm_driver_rp.vArgumentsbar_tableAddress of the Endpoint bar_table structure in BFM sharedmemory. This routine populates the bar_ta

Files Generated for Altera IP CoresFigure 2-3: IP Core Generated FilesThe Quartus II software generates the following output for your IP core.Notes:1.

Location altpcietb_bfm_driver_rp.vArgumentsbar_tableAddress of the Endpoint bar_table structure in BFM sharedmemory.bar_numBAR number to analyze.log2_

Constant DescriptionSHMEM_FILL_QWORD_INCSpecifies a data pattern of incrementing 64-bit qwords(0x0000000000000000, 0x0000000000000001,0x00000000000000

shmem_display Verilog HDL FunctionThe shmem_display Verilog HDL function displays a block of data from the BFM shared memory.Location altpcietb_bfm_dr

Related InformationShared Memory Constants on page 16-40shmem_chk_ok FunctionThe shmem_chk_ok function checks a block of BFM shared memory against a s

Table 16-21: Log MessagesConstant(MessageType)Description Mask BitNoDisplayby DefaultSimulationStops byDefaultMessagePrefixEBFM_MSG_DEBUGSpecifies deb

Constant(MessageType)Description Mask BitNoDisplayby DefaultSimulationStops byDefaultMessagePrefixEBFM_MSG_ERROR_FATAL_TB_ERRUsed for BFM test driver

ebfm_log_stop_sim Verilog HDL FunctionThe ebfm_log_stop_sim procedure stops the simulation.Location altpcietb_bfm_driver_rp.vSyntax Verilog VHDL: retu

Related InformationBFM Log and Message Procedures on page 16-43ebfm_log_open Verilog HDL FunctionThe ebfm_log_open procedure opens a log file of the s

Location altpcietb_bfm_driver_rp.vSyntax string:= himage(vec)ArgumentrangevecInput data type reg with a range of 7:0.ReturnrangestringReturns a 2-digi

Locationaltpcietb_bfm_driver_rp.vSyntax string:= himage(vec)ArgumentrangevecInput data type reg with a range of 63:0.ReturnrangestringReturns a 16-dig

Figure 2-4: Testbench for PCI ExpressPCB Avalon-MM slaveResetHard IP for PCI ExpressAltera FPGAPCB Transaction Layer Data Link LayerPHY MAC Layerx4 P

dimage3This function creates a three-digit decimal string representation of the input argument that can beconcatenated into a larger message string an

Locationaltpcietb_bfm_driver_rp.vReturnrangestringReturns a 5-digit decimal representation of the input argumentthat is padded with leading 0s if nece

chained_dma_test ProcedureThe chained_dma_test procedure is the top-level procedure that runs the chaining DMA read and thechaining DMA writeLocation

Location altpcietb_bfm_driver_rp.vSyntaxdma_wr_test (bar_table, bar_num, use_msi, use_eplast)Argumentsbar_tableAddress of the Endpoint bar_table struc

Location altpcietb_bfm_driver_rp.vSyntaxdma_set_header (bar_table, bar_num, Descriptor_size, direction, Use_msi,Use_eplast, Bdt_msb, Bdt_lab, Msi_numb

Location altpcietb_bfm_driver_rp.vArgumentsrc_addrAddress of the BFM shared memory that is being polled.rc_dataExpected data value of the that is bein

Location altpcietb_bfm_driver_rp.vArgumentsbar_tableAddress of the Endpoint bar_table structure in BFM sharedmemory.bar_numBAR number to analyze.Bus_n

Location altpcietb_bfm_driver_rp.vArgumentsbar_tableAddress of the Endpoint bar_table structure in BFM sharedmemoryallowed_barsOne hot 6 bits BAR sele

Related InformationBFM Log and Message Procedures on page 16-43Debugging SimulationsYou can modify the following default testbench parameter settings

Debugging172014.12.15SubscribeSend FeedbackAs you bring up your PCI Express system, you may face a number of issues related to FPGA configura‐tion, li

Note: Your design must include the Transceiver Reconfiguration Controller IP Core and the Altera PCIeReconfig Driver. Refer to the figure in the Qsys

packets can be transmitted. If you encounter link training issues, viewing the actual data in hardwareshould help you determine the root cause. You ca

Possible Causes Symptoms and Root Causes Workarounds and SolutionsFlow control creditoverflowsDetermine if the credit fieldassociated with the current

Possible Causes Symptoms and Root Causes Workarounds and SolutionsInsufficient Postedcredits released byRoot PortIf a Memory Write TLP istransmitted w

altpcie_<dev>_hip_ast_hwtcl #( .enable_pipe32_sim_hwtcl ( 1 ),Using the PIPE Interface for Gen1 and Gen2 VariantsRunning the simulation in PIPE

Use Third-Party PCIe AnalyzerA third-party logic analyzer for PCI Express records the traffic on the physical link and decodes traffic,saving you the

Transaction Layer Packet (TLP) Header FormatsA2014.12.15SubscribeSend FeedbackThe following figures show the header format for TLPs without a data pay

Figure A-3: Memory Read Request, 64-Bit AddressingMemory Read Request, 64-Bit Addressing3+2+1+0+7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5

Figure A-6: I/O Read RequestI/O Read Request3+2+1+0+7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0Byte 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

Figure A-9: Completion Locked without DataCompletion Locked without Data3+2+1+0+7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0Byte 0

Figure A-12: Configuration Write Request Root Port (Type 1)Configuration Write Request Root Port (Type 1)3+2+1+0+7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5

Parameter Settings32014.12.15SubscribeSend FeedbackAvalon-ST System SettingsTable 3-1: System Settings for PCI ExpressParameter Value DescriptionNumbe

Figure A-15: Completion Locked with DataCompletion Locked with Data3+2+1+0+7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0Byte 0 0 1

Lane Initialization and ReversalB2014.12.15SubscribeSend FeedbackConnected components that include IP blocks for PCI Express need not support the same

Figure B-1: Using Lane Reversal to Solve PCB Routing ProblemsThe following figure illustrates a PCI Express card with ×4 IP Root Port and a ×4 Endpoin

Additional InformationC2014.12.15SubscribeSend FeedbackRevision History for the Avalon-St InterfaceDate Version Changes Made2014.12.15 14.1 Made the f

Date Version Changes MadeMade the following changes to the user guide:• Created separate user guides for variants using the Avalon-MM,Avalon-ST, and A

Date Version Changes Made• Removed references to the ATX PLL. This PLL is not available forArria V• Removed soft reset controller .sdc constraints fro

Date Version Changes Made• Timing models are now final.• Added instructions for running the Single Dword variant.• Corrected definition of test_in[4:1

Typographic ConventionsThe following table shows the typographic conventions this document uses.Table C-1: Visual CueMeaningVisual Cue MeaningBold Typ

Visual Cue Meaningr An angled arrow instructs you to press the Enterkey.1., 2., 3., anda., b., c., and so on Numbered steps indicate a list of items w

Parameter Value DescriptionApplicationInterfaceAvalon-ST 64-bitAvalon-ST 128-bitSpecifies the width of the Avalon-ST interface between theApplication

Parameter Value Description• Minimum RX Buffer credit allocation -performance forreceived requests–This setting configures the minimumPCIe specificati

Parameter Value DescriptionReference clockfrequency100 MHz125 MHzThe PCI Express Base Specification requires a100 MHz ±300 ppm reference clock. The 12

Parameter Value DescriptionSlot clockconfigurationOn/Off When On, indicates that the Endpoint or Root Port uses thesame physical reference clock that

Parameter Possible Values Default Value DescriptionABBANoneRoot Ports and Endpoints that issue requests on theirown behalf. Completion timeouts are sp

Related Information• PCI Express Base Specification 2.1 or 3.0• PCI Express High Performance Reference Design• Creating a System with QsysFeaturesNew

Error ReportingTable 3-4: Error ReportingParameter Value Default Value DescriptionAdvancederrorreporting(AER) On/Off Off When On, enables the Advanced

Parameter Value DescriptionSlot clockconfigurationOn/Off When On, indicates that the Endpoint or Root Port uses thesame physical reference clock that

Parameter Value DescriptionSlot number0-8191Specifies the slot number.Related InformationPCI Express Base Specification Revision 2.1 or 3.0Power Manag

Port Function Parameters Defined Separately for All Port FunctionsBase Address Register (BAR) and Expansion ROM SettingsThe type and size of BARs avai

Base and Limit Registers for Root PortsTable 3-9: Base and Limit Registers for Function 0The following table describes the Base and Limit registers wh

Register Name Range Default Value DescriptionClass code 24 bits 0x00000000 Sets the read-only value of the Class Code register.Address offset: 0x008.S

Parameter Value DescriptionBit RangeTable size [10:0] System software reads this field to determine the MSI-X Tablesize <n>, which is encoded as

Func <n> Legacy InterruptTable 3-13: Func <n> Legacy InterruptParameter Value DescriptionLegacy Interrupt(INTx)INTAINTBINTCINTDNoneWhen se

Interfaces and Signal Descriptions42014.12.15SubscribeSend FeedbackFigure 4-1: Avalon-ST Hard IP for PCI Express Top-Level Signalsrx_st_data[63:0], [1

Related Information• Features on page 1-2• Qsys Design Flow on page 2-2Arria V Hard IP for PCI Express with Avalon-ST Interface to theApplication Laye

Feature Avalon‑ST Interface Avalon‑MM Interface Avalon‑MM DMAGen1 ×1, ×2, ×4, ×8 ×1, ×2, ×4, ×8 x8Gen2 ×1, ×2, ×4 ×1, ×2, ×4 ×464-bit ApplicationLayer

Signal Direction Descriptionrx_st_ready Input Indicates that the Application Layer is ready to accept data. TheApplication Layer deasserts this signa

Signal Direction Descriptionrx_st_bar[7:0] Output The decoded BAR bits for the TLP. Valid for MRd, MWr, IOWR, andIORD TLPs. Ignored for the completion

Signal Direction Descriptionrx_st_be[<n>-1:0] Output Byte enables corresponding to the rx_st_data. The byte enablesignals only apply to PCI Expr

Data Alignment and Timing for the 64‑Bit Avalon‑ST RX InterfaceTo facilitate the interface to 64-bit memories, the Arria V Hard IP for PCI Express ali

Packet TLPData1 pcie_data_byte7, pcie_data_byte6, pcie_data_byte5, pcie_data_byte4Data2 pcie_data_byte11, pcie_data_byte10, pcie_data_byte9, pcie_data

Figure 4-4: 64-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-Dword Header TLPs with QwordAligned AddressIn the following figure, rx_st_be[7

Figure 4-6: 4-Bit Avalon-ST Interface Back-to-Back TransmissionThe following figure illustrates back-to-back transmission on the 64-bit Avalon-ST RX i

Data Alignment and Timing for the 128‑Bit Avalon‑ST RX InterfaceFigure 4-7: 128-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-Dword Header

Figure 4-8: 128-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-Dword Header TLPs with non-Qword Aligned AddressesThe following figure shows

Figure 4-10: 128-Bit Avalon-ST rx_st_data Cycle Definition for 4-Dword Header TLPs with QwordAligned AddressesThe following figure shows the mapping o

Feature Avalon‑ST Interface Avalon‑MM Interface Avalon‑MM DMARequests that cross 4KByte addressboundary (transparentto the ApplicationLayer)Not suppor

Figure 4-12: 128-Bit Avalon-ST Interface Back-to-Back TransmissionThe following figure illustrates back-to-back transmission on the 128-bit Avalon-ST

Table 4-4: 64- or 128‑Bit Avalon-ST TX DatapathSignal Direction Descriptiontx_st_data[<n>-1:0]Input Data for transmission. Transmit data bus. Re

Signal Direction Descriptiontx_st_valid Input Clocks tx_st_data to the core when tx_st_ready is alsoasserted. Between tx_st_sop and tx_st_eop, tx_st_v

Signal Direction Descriptiontx_cred_datafcp[11:0]Output Data credit limit for the FC posted writes. Each credit is 16 bytes.tx_cred_fchipcons[5:0]Outp

Signal Direction Descriptiontx_cred_hdrfcp[7:0]O Header credit limit for the FC posted writes. Each credit is 20bytes.ko_cpl_spc_header[7:0]Output The

Data Alignment and Timing for the 64‑Bit Avalon‑ST TX InterfaceFigure 4-14:The following figure illustrates the mapping between Avalon-ST TX packets a

Data0 = {pcie_data_byte3, pcie_data_byte2, pcie_data_byte1, pcie_data_byte0}Data1 = {pcie_data_byte7, pcie_data_byte6, pcie_data_byte5, pcie_data_byte

Figure 4-19: 64-Bit Back-to-Back Transmission on the TX InterfaceThe following figure illustrates back-to-back transmission of 64-bit packets with no

Figure 4-21: 128-Bit Avalon-ST tx_st_data Cycle Definition for 3-Dword Header TLP with non-QwordAligned AddressThe following figure shows the mapping

Header 3 Data 2Header 2 Data 1Data nHeader 1 Data 0Data n-1Header 0Data n-2pld_clktx_st_validtx_st_data[127:96]tx_st_data[95:64]tx_st_data[63:32]tx_st

Item DescriptionOrdering Codes No ordering code is requiredProduct IDs There are no encrypted files for the Arria V Hard IPfor PCI Express. The Produc

pld_clktx_st_data[127:0]tx_st_soptx_st_eoptx_st_emptytx_st_readytx_st_validtx_st_err000 CC... CC... CC... CC... CC... CC... CC... CC... CC... CC... CC

Clock SignalsTable 4-5: Clock SignalsSignal Direction DescriptionrefclkInput Reference clock for the IP core. It must have the frequencyspecified unde

Table 4-6: Reset SignalsSignal Direction DescriptionnporInput Active low reset signal. In the Altera hardware example designs,npor is the OR of pin_pe

Signal Direction Descriptioneven if the VVCCPGM of the bank is not 3.3V if the following 2conditions are met:• The input signal meets the VIH and VIL

Signal Direction Descriptionpld_core_readyInput When asserted, indicates that the Application Layer is ready foroperation and is providing a stable cl

Signal Direction Descriptioncurrentspeed[1:0]Output Indicates the current speed of the PCIe link. The followingencodings are defined:• 2b’00: Undefine

Error SignalsThe following table describes the ECC error signals. These signals are all valid for one clock cycle. Theyare synchronous to coreclkout_h

Interrupts for EndpointsRefer to Interrupts for detailed information about all interrupt mechanisms.Table 4-9: Interrupt Signals for EndpointsSignal D

Interrupts for Root PortsTable 4-10: Interrupt Signals for Root PortsSignal Direction Descriptionint_status[3:0]Output These signals drive legacy inte

appropriate completion status value for non-posted requests. Refer to Error Handling for information onerrors that are automatically detected and hand

ConfigurationsThe Arria V Hard IP for PCI Express includes a full hard IP implementation of the PCI Express stackcomprising the following layers:• Phy

Signal DirectionDescription• cpl_err[4]: Unsupported Request (UR) error for posted TLP.The Application Layer asserts this signal to treat a posted req

Related InformationTransaction Layer Errors on page 8-3Transaction Layer Configuration Space SignalsTable 4-12: Configuration Space SignalsThese signa

Signal Direction DescriptionInput • [0]: Attention button pressed. This signal should be assertedwhen the attention button is pressed. If no attention

tl_cfg_sts Configuration Space Register Description[58:54] Func1[68:64] Func2[78:74] Func3[88:84] Func4[98:94] Func5[108:104] Func6[118:114] Func7Link

tl_cfg_sts Configuration Space Register Description[30] Link Status 2 Reg[0] Current de-emphasis level.[29:25] Status Reg[15:11] Records the following

Configuration Space Register AccessThe tl_cfg_ctl signal is a multiplexed bus that contains the contents of Configuration Space registers asshown in t

Register Width Direction Descriptioncfg_slot_ctrl16 Output cfg_slot_ctrl[15:0] is the Slot Status of the PCIExpress capability structure. This registe

Register Width Direction Descriptioncfg_msi_addr64 Output cfg_msi_add[63:32] is the message signaledinterrupt (MSI) upper message address. cfg_msi_add

Register Width Direction Descriptioncfg_tcvcmap24 Output Configuration traffic class (TC)/virtual channel(VC) mapping. The Application Layer uses this

Bit(s) Field Description[6:4] multiple messageenableThis field indicates permitted values for MSI signals. For example,if “100” is written to this fie

Figure 1-3: PCI Express Application with an Endpoint Using the Multi-Function CapabilityThe following figure shows a PCI Express link between two Alte

Figure 4-30: Local Management InterfaceConfiguration Space128 32-bit registers(4 KBytes)LMI32lmi_doutlmi_ack15lmi_addr32lmi_dinlmi_rdenlmi_wrenpld_clk

Signal Direction Descriptionlmi_rdenInput Read enable input.lmi_wrenInput Write enable input.lmi_ackOutput Write execution done/read data valid.lmi_ad

Power Management SignalsTable 4-17: Power Management SignalsSignal Direction Descriptionpme_to_crInput Power management turn off control register.Root

Signal Direction Descriptionpm_data[9:0]Input Power Management Data.This bus indicates power consumption of the component. Thisbus can only be impleme

Bits Field Description[15]PME_statusWhen set to 1, indicates that the function would normally assertthe PME# message independently of the state of the

Transceiver ReconfigurationDynamic reconfiguration compensates for variations due to process, voltage and temperature (PVT).Among the analog settings

Serial Interface SignalsTable 4-21: Serial Interface SignalsIn the following table, <n> = 1, 2, 4, or 8.Signal Direction Descriptiontx_out[<n

Figure 4-35: Arria V Transceiver Bank and Hard IP for PCI Express IP Core Locations in Arria V GX and GTDevicesCh5Ch4Ch3Ch2Ch1Ch0Ch5Ch4Ch3Ch2Ch1Ch0Ch5

Figure 4-36: Arria V Transceiver Bank and Hard IP for PCI Express IP Core Locations in Arria V SX and STDevicesCh5Ch4Ch3Ch2Ch1Ch0Ch5Ch4Ch3Ch2Ch1Ch0Ch5

For more comprehensive information about Arria V transceivers, refer to the Transceiver Banks section inthe Transceiver Architecture in Arria V Device

PCIe LinkPCIe Hard IPRPSwitchPCIeHard IPRPUser ApplicationLogicPCIe Hard IPEPPCIe LinkPCIe LinkUser ApplicationLogicAltera FPGA with Hard IP for PCI E

Table 4-23: Hard IP Reconfiguration SignalsSignal Direction Descriptionhip_reconfig_clkInputhip_reconfig_rst_nInput Active-low Avalon-MM reset. Resets

Figure 4-38: Hard IP Reconfiguration Bus Timing of Read-Only Registersavmm_clkhip_reconfig_rst_nuser_modeser_shift_loadinterface_selavmm_wravmm_wrdata

Signal Direction Descriptiontxdetectrx0 Output Transmit detect receive <n>. This signal tells the PHY layer tostart a receive detection operatio

Signal Direction Descriptionrxelecidle0 (1)Input Receive electrical idle <n>. When asserted, indicates detection ofan electrical idle.rxstatus0[

Signal Direction Descriptionsim_pipe_rate[1:0]Output The 2-bit encodings have the following meanings:• 2’b00: Gen1 rate (2.5 Gbps)• 2’b01: Gen2 rate (

Test SignalsTable 4-25: Test Interface SignalsThe test_in bus provides run-time control and monitoring of the internal state of the IP core.Signal Dir

Registers52014.12.15SubscribeSend FeedbackCorrespondence between Configuration Space Registers and the PCIeSpecificationTable 5-1: Correspondence betw

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification0x170:0x17C Reserved N/A0x180:0x1FC Virtual channel arbit

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification0x018 Base Address 2Secondary Latency Timer, Subordinate

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification0x058 Message Upper Address MSI and MSI-X Capability Stru