Altera Hybrid Memory Cube Controller Manuel d'utilisateur télécharger pdf (Page 25)

In addition, the I

C master module must provide the following two signals to connect to the HMC

Controller IP core:

• An input signal that accepts requests to load the configuration registers of the HMC device. You must

connect this signal to the HMC Controller IP core i2c_load_registers output signal. If multiple

HMC Controller IP cores connect to the same HMC device, you must connect this input signal to the

AND of the individual HMC Controller IP core i2c_load_registers output signals. You must

provide the AND function.

• An output signal that indicates successful completion of the configuration register load sequence. The

C master must implement this signal with the following behavior:

1. Deassert this signal when coming out of reset.

2. Assert this signal after writing Init Continue to the HMC device REGISTER REQUEST commands

3. Deassert this signal in response to the falling edge of the input signal described above.

You must connect this signal to the HMC Controller IP core i2c_registers_loaded input signal. If

multiple HMC Controller IP cores connect to the same HMC device, you must connect this signal to

the i2c_registers_loaded signals of all of the HMC Controller IP cores.

For information about the required register configuration sequence, you must refer to the data sheet of

the HMC device that is connected to your HMC Controller IP core. Recall that the HMC Controller IP

core operates in Response Open Loop Mode, and you must configure the HMC device to communicate

correctly with the IP core in this mode. In addition, because the IP core does not support the TGA field,

you must configure the HMC device to respond to every non-posted Write request with a Write response

packet.

Related Information

• HMC Controller IP Core Example Design on page 6-1

The HMC Controller example design provides an example I

C master module and demonstrates how

to connect it to your HMC Controller IP core.

• Interface to External I2C Master on page 3-3

• Signals on the Interface to the I2C Master on page 4-9

Describes the signals on this interface and the four-way handshaking protocol that the HMC

Controller IP core implements and that the I

C master must implement for correct IP core function‐

ality.

• HMC Specification 1.1

The Power-On and Initialization section of the HMC specification describes the initialization sequence

requirements.

Simulating Altera IP Cores in other EDA Tools

The Quartus II software supports RTL and gate-level design simulation of Altera IP cores in supported

EDA simulators. Simulation involves setting up your simulator working environment, compiling

simulation model libraries, and running your simulation.

You can use the functional simulation model and the testbench or example design available with your IP

core for simulation. When you click the Example Design button, the functional simulation model and

testbench files are generated in a location you specify. By default, if you do not modify the target location,

they are generated in a project subdirectory. This directory includes scripts to compile and run the

2-16

Simulating Altera IP Cores in other EDA Tools

UG-01152

2015.05.04

Altera Corporation

Getting Started with the HMC Controller IP Core

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Altera Hybrid Memory Cube Controller Manuel d'utilisateur Page 25

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