Altera Hybrid Memory Cube Controller Manuel d'utilisateur Page 63
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- Table des matières
- MARQUE LIVRES
- User Guide 1
- Contents 2
- Altera Corporation 3
- Controller IP Core 4
- Device Family Support 7
- IP Core Verification 7
- Simulation 8
- Hardware Testing 8
- Device Speed Grade Support 9
- Release Information 9
- Related Information 10
- OpenCore Plus IP Evaluation 11
- UG-01152 12
- 2015.05.04 12
- Pin Constraints 18
- Required External Blocks 19
- Adding the External PLL 20
- HMC Controller IP Core 22
- Adding the External I 24
- C Master Module 24
- Quartus II 26
- Design Flow 26
- Gate-Level Simulation 26
- RTL Simulation 26
- Understanding the Testbench 27
- Functional Description 29
- Interfaces Overview 30
- Interface to External I 31
- C Master 31
- Status and Debug Interface 31
- Clocking and Reset Structure 32
- Initialization 33
- M20K ECC Support 34
- Flow Control 35
- Testing Features 36
- Application Interface Signals 38
- HMC Interface Signals 45
- Status and Debug Signals 48
- Clock and Reset Signals 49
- Code Description 53
- CONTROL Register 54
- XCVR_STATUS Register 55
- LANE_STATUS Register 55
- LINK_STATUS Register 56
- ERROR_RESPONSE Register 57
- Interrupt Related Registers 57
- Bits Field Name Type Value on 58
- Description 58
- M20K ECC Support on page 3-6 63
- Subscribe 64
- Send Feedback 64
- Arria 10 Device 65
- Switch Function Setting 66
- LED Color Meaning When Lit 66
- Additional Information 67
- Typographic Conventions 68
- Visual Cue Meaning 69
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