Altera MAX 10 Clocking and PLL Manuel d'utilisateur

MAX 10 Clocking and PLL User GuideSubscribeSend FeedbackUG-M10CLKPLL2015.05.04101 Innovation DriveSan Jose, CA 95134www.altera.com

Figure 2-2: GCLK Network Sources for 10M16, 10M25, 10M40, and 10M50 DevicesDPCLK2DPCLK3DPCLK0DPCLK1CLK[0,1][p,n] CLK[2,3][p,n]GCLK[0..4] GCLK[5..9]CL

Input DescriptionDPCLK pins DPCLK pins are bidirectional dual function pins thatare used for high fan-out control signals, such asprotocol signals, TR

Each PLL generates five clock outputs through the c[4..0] counters. Two of these clocks can drive theGCLK through a clock control block.From the Clock

Related Information• ALTCLKCTRL Parameters on page 5-1• ALTCLKCTRL Ports and Signals on page 5-2Clock Enable SignalsThe MAX 10 devices support clkena

Related Information• Guideline: Clock Enable Signals on page 3-1• ALTCLKCTRL Parameters on page 5-1• ALTCLKCTRL Ports and Signals on page 5-2Internal

Phase-Frequency Detector (PFD)The PFD has inputs from the feedback clock, fFB, and the input reference clock, fREF. The PLL comparesthe rising edge of

PLL FeaturesTable 2-4: MAX 10 PLL FeaturesFeature SupportC output counters 5M, N, C counter sizes 1 to 512 (2)Dedicated clock outputs 1 single-ended o

Figure 2-8: PLL Locations for 10M02 DeviceBank 8Bank 3Bank 1Bank 2Bank 6Bank 5PLL 1 (1)PLL 2 (2)Notes:(1) Available on all packages except V36 package

Figure 2-10: PLL Locations for 10M16, 10M25, 10M40 and 10M50 DevicesBank 8Bank 1ABank 2Bank 6Bank 5PLL 1PLL 2 (1)Bank 7Bank 3 Bank 4Bank 1BPLL 3 (1)PL

PLL Counter Output GCLKPLL2_C1 GCLK[6,9,11,14]PLL2_C2 GCLK[5,7,10,12]PLL2_C3 GCLK[6,8,11,13]PLL2_C4 GCLK[7,9,12,14]PLL3_C0(5)GCLK[0,3,10,13]PLL3_C1(5)

ContentsMAX 10 Clocking and PLL Overview... 1-1Clock Networks Overview...

lockedThe locked output indicates that the PLL has locked onto the reference clock and the PLL clock outputsare operating at the desired phase and fre

Source Synchronous ModeIf the data and clock arrive at the same time at the input pins, the phase relationship between the data andclock remains the s

Figure 2-13: Example of Phase Relationship Between the PLL Clocks in No Compensation ModePLL ReferenceClock at the Input PinPLL Clock at theRegister C

Zero-Delay Buffer ModeIn zero-delay buffer (ZDB) mode, the external clock output pin is phase-aligned with the clock input pinfor zero delay through t

Figure 2-16: PLL External Clock OutputC0C1C2C4C3PLL #clkena 1 (1)clkena 0 (1)PLL #_CLKOUTp (2)PLL #_CLKOUTn (2)Notes:(1) These external clock enable s

ADC Clock Input from PLLOnly the C0 output counter from PLL1 and PLL3 can drive the ADC clock.Counter C0 has dedicated path to the ADC clock input.Spr

• Charge Pump and Loop Filter on page 4-13Provides more information about the PLL components to update PLL bandwidth in real time.• Programmable Bandw

Figure 2-18: Example of Delay Insertion Using VCO Phase Output and Counter Delay TimeThe observations in this example are as follows:• CLK0 is based o

• Dynamic Phase Configuration Parameter Settings on page 6-4Provides more information about the ALTPLL IP core parameter settings in the Quartus II so

Figure 2-20: Automatic Clock Switchover Circuit Block DiagramThis figure shows a block diagram of the automatic switchover circuit built into the PLL.

Guideline: PLL Cascading...3-3Guideline: C

When using automatic clock switchover mode, the following requirements must be satisfied:• Both clock inputs must be running when the FPGA is configur

You must choose the backup clock frequency and set the M, N, and C counters so that the VCO operateswithin the recommended frequency range.The followi

If inclk0 and inclk1 have different frequencies and are always running, the minimum amount of timefor which clkswitch signal is high must be greater t

The following PLL components are configurable in real time:• Pre-scale counter (N)• Feedback counter (M)• Post-scale output counters (C0-C4)• Charge p

The counter settings are updated synchronously to the clock frequency of the individual counters.Therefore, not all counters update simultaneously.The

MAX 10 Clocking and PLL DesignConsiderations32015.05.04UG-M10CLKPLLSubscribeSend FeedbackClock Networks Design ConsiderationsGuideline: Clock Enable S

Internal Oscillator Design ConsiderationsGuideline: Connectivity RestrictionsYou cannot drive the PLLs with internal oscillator.PLLs Design Considerat

The ALTPLL IP core does not have a dedicated output enable port. You can disable the PLL output usingthe areset signal to disable the PLL output count

• The phase relationship between the input clock to the PLL and output clock from the PLL is importantin your design. Assert areset for 10 ns after pe

MAX 10 Clocking and PLL ImplementationGuides42015.05.04UG-M10CLKPLLSubscribeSend FeedbackALTCLKCTRL IP CoreThe clock control block (ALTCLKCTRL) IP cor

Internal Oscillator Parameters...8-1In

Use the following features to help you quickly locate and select an IP core:• Filter IP Catalog to Show IP for active device family or Show IP for all

1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.The parameter editor appears.2. Specify a t

Figure 4-2: IP Parameter EditorView IP portand parameter detailsApply preset parameters forspecific applicationsSpecify your IP variation nameand targ

Figure 4-3: IP Core Generated FilesNotes:1. If supported and enabled for your IP variation2. If functional simulation models are generated<Project

IP Catalog and Parameter EditorThe Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize andintegrate IP cores

Figure 4-4: Quartus II IP CatalogSearch for installed IP coresDouble-click to customize, right-click for detailed informationShow IP only for target d

• Optionally select preset parameter values if provided for your IP core. Presets specify initialparameter values for specific applications.• Specify

frequency values in the PLL Summary report located under the Resource Section of the Fitter folder in theCompilation Report.The Quartus II software do

Programmable Bandwidth with Advanced ParametersAn advanced level of control is also possible for precise control of the PLL loop filter characteristic

Figure 4-6: PLL Reconfiguration Scan Chain Functional SimulationscandatascanclkscanclkenascandataoutconfigupdatescandonearesetDn_oldD0_old DnD0DnLSBWh

MAX 10 Clocking and PLL Overview12015.05.04UG-M10CLKPLLSubscribeSend FeedbackClock Networks OverviewMAX® 10 devices support global clock (GCLK) networ

cycle, you must set the rselodd control bit to 1 to achieve this duty cycle despite an odd division factor.When you set rselodd = 1, subtract 0.5 cycl

Figure 4-7: PLL Component Scan Chain OrderDATAINC1C2C3C4DATAOUTMSBLF CPLSBN M C0Figure 4-8: PLL Post-Scale Counter Scan Chain Bit OrderDATAINrbypassHB

LFR[4] LFR[3] LFR[2] LFR[1] LFR[0] Setting (Decimal)1 0 1 0 0 201 1 0 0 0 241 1 0 1 1 271 1 1 0 0 281 1 1 1 0 30Table 4-4: Loop Filter High Frequency

Dynamic Phase Configuration ImplementationTo perform one dynamic phase shift step, perform the following steps:1. Set PHASEUPDOWN and PHASECOUNTERSELE

• ALTPLL_RECONFIG Parameters on page 7-1Provides more information about the ALTPLL_RECONFIG IP core parameter settings in the QuartusII software.• PLL

When using Advanced Parameters, the PLL wrapper file (<ALTPLL_instantiation_name>.v or<ALTPLL_instantiation_name>.vhd) is written in a for

ALTPLL_RECONFIG IP CoreThe ALTPLL_RECONFIG IP core implements reconfiguration logic to facilitate dynamic real-timereconfiguration of PLLs. You can us

Figure 4-11: Quartus II IP CatalogSearch for installed IP coresDouble-click to customize, right-click for detailed informationShow IP only for target

• Optionally select preset parameter values if provided for your IP core. Presets specify initialparameter values for specific applications.• Specify

Figure 4-13: IP Core Generated FilesNotes:1. If supported and enabled for your IP variation2. If functional simulation models are generated3. Ignore t

• PLL cascading• Reference clock switchover• Drive the analog-to-digital converter (ADC) clock1-2PLLs OverviewUG-M10CLKPLL2015.05.04Altera Corporation

IP Catalog and Parameter EditorThe Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize andintegrate IP cores

Figure 4-14: Quartus II IP CatalogSearch for installed IP coresDouble-click to customize, right-click for detailed informationShow IP only for target

• Optionally select preset parameter values if provided for your IP core. Presets specify initialparameter values for specific applications.• Specify

Figure 4-16: IP Core Generated FilesNotes:1. If supported and enabled for your IP variation2. If functional simulation models are generated<Project

ALTCLKCTRL IP Core References52015.05.04UG-M10CLKPLLSubscribeSend FeedbackALTCLKCTRL ParametersTable 5-1: ALTCLKCTRL IP Core Parameters for MAX 10 Dev

Parameter Value DecriptionEnsure glitch-freeswitchover implementa‐tionOn or OffTurn on this option to implement a glitch-freeswitchover when you use m

Port Name Condition Descriptioninclk[] RequiredClock input of the clock buffer.Input port [1 DOWNTO 0] wide.You can specify up to two clock inputs, in

ALTPLL IP Core References62014.12.15UG-M10CLKPLLSubscribeSend FeedbackALTPLL ParametersThe following tables list the IP core parameters applicable to

Related InformationClock Feedback Modes on page 2-14PLL Control Signals Parameter SettingsThe parameter settings for the control signals are located o

Clock Switchover Parameter SettingsThe parameter settings for clock switchover feature are located on the Clock switchover page of theALTPLL IP core p

MAX 10 Clocking and PLL Architecture andFeatures22015.05.04UG-M10CLKPLLSubscribeSend FeedbackClock Networks Architecture and FeaturesGlobal Clock Netw

• Guideline: Clock Switchover on page 3-3PLL Dynamic Reconfiguration Parameter SettingsThe parameter settings for the normal dynamic reconfiguration s

Related Information• Programmable Phase Shift on page 2-20• Dynamic Phase Configuration Implementation on page 4-15Output Clocks Parameter SettingsThe

Parameter Value DescriptionClock duty cycle (%) — Set the duty cycle of the output clock signal.Per Clock FeasibilityIndicators—Indicate output clocks

Port Name(10)Condition Descriptioninclk[]Required The clock inputs that drive the clock network.If more than one inclk[] port is created, you mustuse

Table 6-8: ALTPLL Output Ports for MAX 10 DevicesPort Name(11)Condition DescriptionactiveclockOptional Specifies which clock is the primary reference

Port Name(11)Condition DescriptionlockedOptional This output port acts as an indicator when the PLLhas reached phase-locked. The locked port stayshigh

Related InformationPLL Control Signals on page 2-136-10ALTPLL Ports and SignalsUG-M10CLKPLL2014.12.15Altera CorporationALTPLL IP Core ReferencesSend F

ALTPLL_RECONFIG IP Core References72015.05.04UG-M10CLKPLLSubscribeSend FeedbackALTPLL_RECONFIG ParametersTable 7-1: ALTPLL_RECONFIG IP Core Parameters

Page Parameter Value DescriptionEDASimulation Libraries — Specifies the libraries for functionalsimulation.Generate netlist On, Off Turn on this optio

Port Name Condition DescriptionresetRequired Asynchronous reset input to the IP core.Altera recommends that you reset this IP core before firstuse to

Clock ResourcesTable 2-1: MAX 10 Clock ResourcesClock Resource Device Number of ResourcesAvailableSource of Clock ResourceDedicated clock input pins•

Port Name Condition Descriptionread_paramOptional Reads the parameter specified with the counter_type andcounter_param ports from cache and fed to the

Port Name Condition DescriptionreconfigRequired Specifies that the PLL should be reconfigured with thePLL settings specified in the current cache.When

Table 7-3: ALTPLL_RECONFIG Output Ports for MAX 10 DevicesPort Name Condition Descriptiondata_out[]Optional Data read from the cache when read_param i

Port Name Condition Descriptionpll_scanclkenaOptional This port acts as a clock enable for the scanclk port onthe PLL to be reconfigured.Reconfigurati

Table 7-5: counter_param[2..0] Settings for MAX 10 DevicesCounter Type Counter Param Binary Decimal Width (bits)Regular counters (C0 -C4)High count 00

Internal Oscillator IP Core References82015.05.04UG-M10CLKPLLSubscribeSend FeedbackInternal Oscillator ParametersTable 8-1: Internal Oscillator IP Cor

Additonal Information for MAX 10 Clockingand PLL User GuideA2015.05.04UG-M10CLKPLLSubscribeSend FeedbackDocument Revision History for MAX 10 Clocking

CLK Pin GCLKCLK6n(1)GCLK[16,17]CLK7p(1)GCLK[16,18,19]CLK7n(1)GCLK[15,18]DPCLK0 GCLK[0,2]DPCLK1 GCLK[1,3,4]DPCLK2 GCLK[5,7]DPCLK3 GCLK[6,8,9]Figure 2-1