Altera Hybrid Memory Cube Controller Manuel d'utilisateur

Hybrid Memory Cube Controller IP CoreUser GuideLast updated for Altera Complete Design Suite: 15.0SubscribeSend FeedbackUG-011522015.05.04101 Innovati

Getting Started with the HMC Controller IPCore22015.05.04UG-01152SubscribeSend FeedbackThe following information explains how to install, parameterize

Installing and Licensing IP CoresThe Altera IP Library provides many useful IP core functions for your production use without purchasingan additional

1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.The parameter editor appears.2. Specify a t

Parameter Type Range Default Setting Parameter DescriptionCDRreferenceclockString • 312.5 MHz(at 10 Gbpsonly)• 390.625 MHz(at 12.5 Gbpsonly)• 125 MHz•

Parameter Type Range Default Setting Parameter DescriptionEnableM20K ECCsupportBoolean • True• FalseFalseSpecifies whether the IP coresupports the ECC

Figure 2-2: Default RX and TX Mapping Parameter ValuesFPG AHMC ControllerHybrid Memory Cubehmc_lxtx[0] LxRX[0]LxTX[0]hmc_lxrx[0]hmc_lxtx[1] LxRX[1]LxT

Figure 2-3: Non-Default RX Mapping Parameter Value ExampleIf you connect the IP core hmc_lxrx[2:0] input signals according to the table, and connect a

Figure 2-4: Non-Default TX Mapping Parameter Value ExampleIf you connect the HMC Controller IP core hmc_lxtx[2:0] output signals according to the tabl

Figure 2-5: IP Core Generated Files<your_ip >.cmp - VHDL component declaration file<your_ip >.ppf - XML I/O pin information file<your

When you integrate your HMC Controller IP core instance in your design, you must make appropriatepin assignments. You can create a virtual pin to avoi

ContentsAbout the Altera Hybrid Memory Cube Controller IP Core...1-1HMC Controller IP Core Supported Features...

Figure 2-6: Required External BlocksThe required external blocks appear darker than the other blocks in the figure. The external TX PLL IPcore configu

In the transceiver PLL parameter editor, you must follow the instructions in the Arria 10 Transceiver PHYUser Guide to configure the PLL IP core in th

Figure 2-7: Transceiver PLL Connections Example with xN Bonding SchemeExample connections between a full-width HMC Controller IP core and a single ATX

Figure 2-8: Transceiver PLL Connections Example with PLL Feedback Compensation SchemeExample connections between a full-width HMC Controller IP core a

HMC Controller Signal Connects to TX PLL Signalpll_powerdown output signal pll_powerdown reset pin of the external PLLs for all of theHMC lanes.pll_ca

In addition, the I2C master module must provide the following two signals to connect to the HMCController IP core:• An input signal that accepts reque

testbench. For a complete list of models or libraries required to simulate your IP core, refer to the scriptsgenerated with the testbench.Figure 2-9:

Understanding the TestbenchAltera provides an example design with the HMC Controller IP core. The example design is available bothfor simulation of yo

Note: You must specify <HMC BFM directory> as an absolute path.Simulator License Command LineMentor GraphicsQuestaSimmake vsim HMC_MODEL=<HMC

Functional Description32015.05.04UG-01152SubscribeSend FeedbackThe Altera HMC Controller MegaCore IP core enables easy access to external HMC devices.

HMC Controller IP Core Signals...4-1Application Interface Signals...

The HMC Controller IP core includes the following components:• Two data paths, an HMC TX path and an HMC RX path. Each path includes a link layer modu

Interface to External I2C MasterThe HMC Controller IP core requires that you instantiate an external I2C master module in your design.This external I2

External PLL InterfaceThe HMC Controller IP core requires that you generate one or more external transceiver PLL IP coresand connect one of the PLL IP

Figure 3-2: HMC Controller IP Core Clocking DiagramTX PLLpll_refclk0HMC Controller IP CoreTransceiverx16core_clkreconfig_clktx_bonding_clocks[95:90]tx

When you initialize the HMC link, recall the following HMC Controller IP core requirements:• The HMC Controller IP core operates in Response Open Loop

This feature enhances data reliability but increases request-to-response latency and resource utilization.Enabling this feature might reduce the maxim

Response Packet Field Error Indication INTERRUPT_STATUS Register BitSEQ Unexpected value SEQ ErrorThe HMC Controller IP core also checks the ERRSTAT f

Related Information• Transceiver Reconfiguration Signals on page 4-13• CONTROL Register on page 5-2• Arria 10 Transceiver PHY User GuideInformation ab

HMC Controller IP Core Signals42015.05.04UG-01152SubscribeSend FeedbackThe HMC Controller IP core communicates with other design components through mu

cycles. In half-width variations, the maximum payload size limits the interface to data bursts of 4 or fewercore_clk clock cycles. Write requests and

About the Altera Hybrid Memory CubeController IP Core12015.05.04UG-01152SubscribeSend FeedbackThe Hybrid Memory Cube (HMC) specification defines a new

Signal Name Direction Descriptiondp_req_validInput Indicates that the transaction is valid—all input signalshave valid values. The HMC Controller IP c

Signal Name Direction Descriptiondp_req_data[511:0] (for full-width IP cores)dp_req_data[255:0] (for half-width IP cores)Input Write data.The applicat

Figure 4-2: HMC Controller IP Core to RX ApplicationThe HMC Controller IP core acts as a source and the client acts as a sink in the receive direction

Signal Name Direction Descriptiondp_rsp_size[2:0]Output Indicates the size of the payload associated with thisresponse. If the current response is a R

Signal Name Direction Descriptiondp_rsp_errorOutput Indicates that the corresponding request completed withan error and will not be retried automatica

When the HMC Controller IP core deasserts the dp_req_ready signal, user logic maintains the currentvalues until a full clock cycle after the IP core r

Related InformationHMC Specification 1.1The HMC specification is available for download from the Hybrid Memory Cube Consortium web page.Signals on the

Related InformationHMC Controller IP Core Example Design on page 6-1The HMC Controller example design includes an I2C master module that correctly imp

Related Information• Control and Status Register Interface on page 3-3• HMC Controller IP Core Register Map on page 5-1• Interrupt Related Registers o

Clock and Reset SignalsTable 4-7: HMC Controller IP Core Clock and Reset SignalsThe HMC Controller IP core has a single clock domain outside of the tr

Related InformationHMC Specification 1.1The HMC specification is available for download from the Hybrid Memory Cube Consortium web page.HMC Controller

Clock NameDirectionDescriptioncore_clk OutputMaster clock for the HMC Controller IP core. Thetransceiver generates core_clk. The frequency of core_clk

Signal Name Direction Descriptionreconfig_writedata[31:0]Input Write datareconfig_readdata[31:0]Output Read dataThe data on reconfig_readdata[31:0] is

Signals on the Interface to the External PLLsTable 4-9: HMC Controller IP Core External PLL Interface SignalsThe HMC Controller IP core requires that

HMC Controller IP Core Register Map52015.05.04UG-01152SubscribeSend FeedbackThe HMC Controller IP core internal registers are 32 bits wide and are acc

Offset Register Name Location of Additional Information0x20 INTERRUPT_STATUSInterrupt Related Registers0x24 INTERRUPT_ENABLE0x28 GLOBAL_INTERRUPT_ENAB

XCVR_STATUS RegisterTable 5-4: HMC Controller IP Core XCVR_STATUS Register at Offset 0x08Individual transceiver status in HMC link, ordered by transce

Bits Field Name Type Value onResetDescription7:0(half-width IPcore)DescramSync RO 0x00Each bit indicates whether the descrambler for thecorresponding

ERROR_RESPONSE RegisterTable 5-7: HMC Controller IP Core ERROR_RESPONSE Register at Offset 0x14The HMC Controller IP core stores the ERRSTAT and CUB f

Table 5-8: HMC Controller IP Core INTERRUPT_STATUS Register at Offset 0x20To clear an interrupt, write the value of 1 to the interrupt bit.Bits Field

Bits Field Name Type Value onResetDescription8 Retry BufferFullW1C 0x0 The IP core sets this interrupt bit if the Retry buffer fills.When the Retry bu

HMC Controller IP Core Supported HMC Transaction TypesThe Altera HMC Controller IP core supports all HMC transactions. The full-width variations requi

Bits Field Name Type Value onResetDescription14 Response QueueECC ErrorEnableRW 0x0 Enables Response Queue ECC Error interrupt.13 FERR_N Enable RW 0x0

Bits Field Name Type Value onResetDescription0 GlobalEnable RW 0x0 Writing the value of 0 to this register field disables allinterrupt sources from as

Table 5-13: HMC Controller IP Core RETRY_BUFFER_ECC_COUNT Register at Offset 0x38Bits Field Name TypeValueonResetDescription31:24 Reserved RO 0x0023:1

Related InformationM20K ECC Support on page 3-6UG-011522015.05.04Error and Retry Statistics Registers5-11HMC Controller IP Core Register MapAltera Cor

HMC Controller IP Core Example Design62015.05.04UG-01152SubscribeSend FeedbackAltera provides a compilation-ready example design with the HMC Controll

Figure 6-1: High Level Block Diagram for the HMC Controller IP Core Example DesignThe example design configures a single ATX PLL in xN bonding mode an

8. Change directory to <example design directory>/example_design/par.9. Select hmcc_example.qpf.10.Click Processing > Start Compilation. The

Additional InformationA2015.05.04UG-01152SubscribeSend FeedbackHMC Controller IP Core User Guide Revision HistoryTable A-1: Document Revision HistoryS

• www.altera.com/training• [email protected]• www.altera.com/literature• [email protected]• [email protected] ConventionsTable A-3

Visual Cue MeaningCourier typeIndicates signal, port, register, bit, block, andprimitive names. For example, data1, tdi, andinput. The suffix n denote

• 128-byte READ response (9-FLIT packet)• MODE READ response (2-FLIT packet)• MODE WRITE response (single FLIT packet)The HMC Controller IP core does

SimulationAltera performs the following tests on the HMC Controller IP core in simulation, using the Micron HMCBFM:• Constrained random tests that cov

Device Speed Grade SupportTable 1-4: Minimum Recommended Device Family Speed Grades Altera recommends that you configure the HMC Controller IP core on