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Arria V Avalon-MM Interface for PCIe SolutionsUser GuideSubscribeSend FeedbackLast updated for Altera Complete Design Suite: 14.1 UG-01105_avmm2014.12

Table 1-5: Performance and Resource Utilization Avalon-MM Hard IP for PCI ExpressData Rate or InterfaceWidthALMs Memory M10K Logic RegistersAvalon-MM

Reset Sequence for Hard IP for PCI Express IP Core and Application LayerFigure 6-2: Hard IP for PCI Express and Application Logic Reset SequenceYour A

Figure 6-3: RX Transceiver Reset Sequencebusy_xcvr_reconfigrx_pll_lockedrx_analogresetltssmstate[4:0]txdetectrx_loopbackpipe_phystatuspipe_rxstatus[2:

For descriptions of the available reset signals, refer to Reset Signals, Status, and Link Training Signals.ClocksThe Hard IP contains a clock domain c

The PCI Express Base Specification requires that the refclk signal frequency be 100 MHz ±300 PPM.The transitions between Gen1 and Gen2 should be glitc

Link Width Maximum Link Rate Avalon Interface Width coreclkout_hip×2Gen2 64125 MHz×4 Gen2 128 125 MHzpld_clkcoreclkout_hip can drive the Application L

Interrupts for Endpoints72014.12.15UG-01105_avmmSubscribeSend FeedbackThe PCI Express Avalon-MM bridge supports MSI or legacy interrupts. The complete

Figure 7-1: Avalon-MM Interrupt Propagation to the PCI Express LinkInterrupt Disable(Configuration Space Command Register [10])Avalon-MM-to-PCI-Expres

Generation of Avalon-MM InterruptsThe generation of Avalon-MM interrupts requires the instantiation of the CRA slave module where theinterrupt registe

Figure 7-2: Block Diagram for Custom Interrupt HandlerMSMSI/MSI-X IRQMSI-X Table EntriesSQsysInterconnectSMPCIe-Avalon-MMBridgeHardIP forPCIeMSI orMSI

Error Handling82014.12.15UG-01105_avmmSubscribeSend FeedbackEach PCI Express compliant device must implement a basic level of error management and can

Link Rate Link Width InterfaceWidthApplication ClockFrequency (MHz)Recommended Speed GradesGen2×1 64 bits125–4,–5×2 64 bits 125 –4,–5×4 128 bits 125 –

Physical Layer ErrorsTable 8-2: Errors Detected by the Physical LayerThe following table describes errors detected by the Physical Layer. Physical Lay

Transaction Layer ErrorsTable 8-4: Errors Detected by the Transaction LayerError Type DescriptionPoisoned TLP received Uncorrectable(non-fatal)This er

Error Type DescriptionIn all cases the TLP is deleted in the Hard IP block andnot presented to the Application Layer. If the TLP is anon-posted reques

Error Type DescriptionUnexpected completion Uncorrectable(non-fatal)This error is caused by an unexpected completiontransaction. The Hard IP block han

Error Type DescriptionMalformed TLP Uncorrectable(fatal)This error is caused by any of the following conditions:• The data payload of a received TLP e

Poisoned TLPs can also set the parity error bits in the PCI Configuration Space Status register.Table 8-5: Parity Error ConditionsStatus Bit Condition

Figure 8-2: Correctable Error Status RegisterThe default value of all the bits of this register is 0. An error status bit that is set indicates that t

IP Core Architecture92014.12.15UG-01105_avmmSubscribeSend FeedbackThe Avalon-MM Arria V Hard IP for PCI Express implements the complete PCI Express pr

Figure 9-1: Arria V Hard IP for PCI Express Using the Avalon-MM InterfaceClockDomainCrossing(CDC)Data LinkLayer(DLL)Transaction Layer (TL)PHYMAC Hard

Related Information• 64- or 128-Bit Avalon-MM Interface to the Application Layer on page 4-1• Avalon Interface SpecificationsClocks and ResetThe PCI E

Getting Started with the Avalon‑MM Arria VHard IP for PCI Express22014.12.15UG-01105_avmmSubscribeSend FeedbackYou can download a design example for t

Related InformationPIPE Interface SignalsData Link LayerThe Data Link Layer is located between the Transaction Layer and the Physical Layer. It mainta

Figure 9-2: Data Link LayerTo Transaction LayerTx Transaction LayerPacket Description & DataTransaction LayerPacket GeneratorRetry BufferTo Physic

• ACK/NAK Packets—The ACK/NAK block handles ACK/NAK DLLPs and generates the sequencenumber of transmitted packets.• Transaction Layer Packet Checker—T

Figure 9-3: Physical Layer ArchitectureScrambler8B10BEncoderLane nTX+ / TX-Scrambler8B10BEncoderLane 0TX+ / TX-Descrambler8B10BDecoderLane nRX+ / RX-E

The PHYMAC block comprises four main sub-blocks:• MAC Lane—Both the RX and the TX path use this block.• On the RX side, the block decodes the Physical

The Avalon-MM bridge provides three possible Avalon-MM ports: a bursting master, an optionalbursting slave, and an optional non-bursting slave. The Av

Figure 9-4: PCI Express Avalon-MM BridgeTransaction LayerPCI ExpressTx ControllerPCI ExpressRx ControllerData Link LayerPhysical LayerPCI Express Mega

Related InformationAvalon-MM RX Master Block on page 9-20Avalon‑MM Bridge TLPsThe PCI Express to Avalon-MM bridge translates the PCI Express read, wri

PCI Express-to-Avalon-MM Read CompletionsThe PCI Express Avalon-MM bridge returns read completion packets to the initiating Avalon-MMmaster in the iss

Related InformationMinimizing BAR Sizes and the PCIe Address Space on page 9-15Avalon-MM-to-PCI Express Read CompletionsThe PCI Express Avalon-MM brid

The design example transfers data between an on-chip memory buffer located on the Avalon-MM sideand a PCI Express memory buffer located on the root co

Figure 9-5: Address Translation in TX and RX Directions For EndpointsTransaction,Data Link,and PHYDMAAvalon-MM32-Bit Byte AddressAvalon-MM32-Bit Byte

Minimizing BAR Sizes and the PCIe Address SpaceFor designs that include multiple BARs, you may need to modify the base address assignmentsauto-assigne

Figure 9-6: Qsys System for PCI Express with Poor Address Space UtilizationThe following figure uses a filter to hide the Conduit interfaces that are

This design is consuming 1.25 GB of PCIe address space when only 276 MBytes are actually required. Thesolution is to edit the address map to place the

Sp[1:0], that specifies 32-bit or 64-bit PCI Express addressing for the translated address. The mostsignificant bits of the Avalon-MM address are used

Figure 9-10: Avalon-MM-to-PCI Express Address TranslationThe following figure depicts the Avalon-MM-to-PCI Express address translation process. In thi

Figure 9-11: Qsys Design Including Completer Only Single Dword Endpoint for PCI ExpressQsys SystemPCI ExpressRoot ComplexPCIe Linkto HostCPUAvalon-MMI

TX BlockThe TX block sends completion information to the Avalon-MM Hard IP for PCI Express which sends thisinformation to the root complex. The TX com

According to the PCI Express Base Specification, if MSI_enable=0 and the Disable Legacy Interruptbit=1 in the Configuration Space Command register (0x

Design Implementation102014.12.15UG-01105_avmmSubscribeSend FeedbackCompleting your design includes additional steps to specify analog properties, pin

Refer to Creating a System with Qsys in volume 1 of the Quartus II Handbook for more information abouthow to use Qsys. For an explanation of each Qsys

You can also enter these commands at the Quartus II Tcl Console. For example, the following commandsets the XCVR_VCCR_VCCT_VOLTAGE to 1.0 V for the pi

Optional Features112014.12.15UG-01105_avmmSubscribeSend FeedbackConfiguration via Protocol (CvP)The Hard IP for PCI Express architecture has an option

CvP has the following advantages:• Provides a simpler software model for configuration. A smart host can use the PCIe protocol and theapplication topo

Table 11-2: ECRC Operation on RX PathECRC Forwarding ECRC Check Enable(5)ECRC Status Error TLP Forward to Application LayerNoNonone No Forwardedgood N

Table 11-3: ECRC Generation and Forwarding on TX PathAll unspecified cases are unsupported and the behavior of the Hard IP is unknown.ECRC Forwarding

Transceiver PHY IP Reconfiguration122014.12.15UG-01105_avmmSubscribeSend FeedbackAs silicon progresses towards smaller process nodes, circuit performa

As this figure illustrates, the reconfig_to_xcvr[ <n> 70-1:0] and reconfig_from_xcvr[ <n> 46-1:0]buses connect the two components. You mus

number of logical interfaces by merging them. Allowing the Quartus II software to merge reconfi‐guration interfaces gives the Fitter more flexibility

Debugging132014.12.15UG-01105_avmmSubscribeSend FeedbackAs you bring up your PCI Express system, you may face a number of issues related to FPGA confi

packets can be transmitted. If you encounter link training issues, viewing the actual data in hardwareshould help you determine the root cause. You ca

The driver performs the following transactions with status of the transactions displayed in the ModelSimsimulation message window:1. Various configura

Reducing Counter Values for Serial SimulationsYou can accelerate simulation by reducing the value of counters whose default values are set for hardwar

BIOS Enumeration IssuesBoth FPGA programming (configuration) and the initialization of a PCIe link require time. Potentially,an Altera FPGA including

Transaction Layer Packet (TLP) Header FormatsA2014.12.15UG-01105_avmmSubscribeSend FeedbackThe following figures show the header format for TLPs witho

Figure A-3: Memory Read Request, 64-Bit AddressingMemory Read Request, 64-Bit Addressing3+2+1+0+7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5

Figure A-6: I/O Read RequestI/O Read Request3+2+1+0+7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0Byte 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

Figure A-9: Completion Locked without DataCompletion Locked without Data3+2+1+0+7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0Byte 0

Figure A-12: Configuration Write Request Root Port (Type 1)Configuration Write Request Root Port (Type 1)3+2+1+0+7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5

Figure A-15: Completion Locked with DataCompletion Locked with Data3+2+1+0+7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0Byte 0 0 1

Lane Initialization and ReversalB2014.12.15UG-01105_avmmSubscribeSend FeedbackConnected components that include IP blocks for PCI Express need not sup

Figure B-1: Using Lane Reversal to Solve PCB Routing ProblemsThe following figure illustrates a PCI Express card with ×4 IP Root Port and a ×4 Endpoin

Understanding Channel Placement GuidelinesArria V transceivers are organized in banks. The transceiver bank boundaries are important for clockingresou

Additional InformationC2014.08.18UG-01105_avmmSubscribeSend FeedbackRevision History for the Avalon-MM InterfaceDate Version Changes Made2014.12.15 14

Date Version Changes Made• Added figure showing connectivity for the Transceiver Reconfigu‐ration Controller and Altera PCIe Reconfig Driver IP Cores

Date Version Changes Made• Clarified that the Avalon-MM Bridge does not generate out-of-order Avalon-MM-to-PCI Express Read Completions even todiffere

Date Version Changes Made• Added definition of nreset_status for variants using theAvalon-MM interface.• In Transaction Layer Routing Rules and Progra

Contact (1)Contact Method AddressProduct literature Website www.altera.com/literatureNontechnical support (general) Email [email protected](software

Visual Cue MeaningInitial Capital Letters Indicate keyboard keys and menu names. Forexample, the Delete key and the Options menu.“Subheading Title” Qu

Visual Cue Meaningw A warning calls attention to a condition or possiblesituation that can cause you injury.The Subscribe button links to the Email Su

9. From the Simulation list, select ModelSim®. From the Format list, select the HDL language youintend to use for simulation.10.Click Next to display

Files Generated for Altera IP CoresFigure 2-3: IP Core Generated FilesThe Quartus II software generates the following output for your IP core.Notes:1.

Related InformationQuartus II Programmer2-8Programming a DeviceUG-01105_avmm2014.12.15Altera CorporationGetting Started with the Avalon‑MM Arria V Har

Datasheet12014.12.15UG-01105_avmmSubscribeSend FeedbackAvalon-MM Interface for PCIe DatasheetAltera® Arria® V FPGAs include a configurable, hardened p

Parameter Settings32014.12.15UG-01105_avmmSubscribeSend FeedbackAvalon-MM System SettingsTable 3-1: System Settings for PCI ExpressParameter Value Des

Parameter Value DescriptionThe Message window of the GUI dynamically updates thenumber of credits for Posted, Non-Posted Headers and Data,and Completi

Base Address Register (BAR) SettingsYou can configure up to six 32-bit BARs or three 64-bit BARs.Table 3-2: BAR RegistersParameter Value DescriptionTy

Register Name Range Default Value DescriptionRevision ID 8 bits 0x00000001 Sets the read-only value of the Revision ID register.Address offset: 0x008.

Parameter Possible Values Default Value Descriptionfunctions this field is reserved and must be hardwired to0x0000b. Four time value ranges are define

Parameter Value Default Value DescriptionECRCcheckingOn/Off Off When On, enables ECRC checking. Sets the read-onlyvalue of the ECRC check capable bit

Parameter Value DescriptionTable size [10:0] System software reads this field to determine the MSI-X Tablesize <n>, which is encoded as <n–1&

Power ManagementTable 3-8: Power Management ParametersParameter Value DescriptionEndpoint L0sacceptablelatencyMaximum of 64 nsMaximum of 128 nsMaximum

Avalon Memory‑Mapped System SettingsTable 3-9: Avalon Memory-Mapped System SettingsParameter Value DescriptionAvalon-MM data width64-bit128-bitSpecifi

Parameter Value DescriptionSingle DW Completer On/OffThis is a non-pipelined version of Completer Onlymode. At any time, only a single request can beo

Refer to the PCI Express High Performance Reference Design for more information about calculatingbandwidth for the hard IP implementation of PCI Expre

Parameter Value DescriptionEnable hard IP status bus On/Off When you turn this option on, your top-level variantincludes the signals necessary to conn

Interfaces and Signal Descriptions42014.12.15UG-01105_avmmSubscribeSend Feedback64- or 128-Bit Avalon-MM Interface to the Application LayerThis chapte

tx_out0[<n>-1:0]rx_in0[<n>-1:0]1-Bit SerialCraReadData_o[31:0]CraWaitRequest_oCraByteEnable_i[3:0]CraChipSelect_iCraAddress_i[13:0]CraRead

Table 4-1: Avalon-MM CRA Slave Interface SignalsSignal Name DirectionDescriptionCraIrq_oOutput Interrupt request. A port request for an Avalon-MM inte

Signal Name Direction DescriptionRxmByteEnable_<n>_o[<w>-1:0]Output Byte enable for write data.RXMBurstCount_<n>_o[6 or5:0]Output Th

Figure 4-1: Simultaneous DMA Read, DMA Write, and Target AccessRxmRead_oRxmReadDataValid_iRxmReadData_i[63:0]RxmResetRequest_oRxmAddress_o[31:0]RxmWai

Table 4-3: Avalon-MM TX Slave Interface SignalsSignal Name Direction DescriptionTxsChipSelect_iInput The system interconnect fabric asserts this signa

Signal Name Direction DescriptionTxsByteEnable_i[<w>-1:0]Input Write byte enable for data. A burst must be continuous.Therefore all intermediate

Clock SignalsTable 4-4: Clock SignalsSignal Direction DescriptionrefclkInput Reference clock for the IP core. It must have the frequencyspecified unde

Table 4-5: Reset SignalsSignal Direction DescriptionnporInput Active low reset signal. In the Altera hardware example designs,npor is the OR of pin_pe

Feature Avalon‑ST Interface Avalon‑MM Interface Avalon‑MM DMARoot port Supported Supported Not SupportedGen1 ×1, ×2, ×4, ×8 ×1, ×2, ×4, ×8 x8Gen2 ×1,

Signal Direction Descriptioneven if the VVCCPGM of the bank is not 3.3V if the following 2conditions are met:• The input signal meets the VIH and VIL

Table 4-6: Status and Link Training SignalsSignal Direction Descriptionderr_cor_ext_rcv Output Indicates a corrected error in the RX buffer. This sign

Signal Direction Descriptionint_status[3:0]Output These signals drive legacy interrupts to the Application Layer asfollows:• int_status[0]: interrupt

Signal Direction Description• 00110: config.Linkwidthstart• 00111: Config.Linkaccept• 01000: Config.Lanenumaccept• 01001: Config.Lanenumwait• 01010: C

Signal Direction DescriptionMsiControl_o[15:0]Output Provides for system software control of MSI as defined in Section6.8.1.3 Message Control for MSI

Figure 4-4: Legacy Interrupt DeassertionclkIntxReq_iIntAck_oPhysical Layer Interface SignalsAltera provides an integrated solution with the Transactio

The ×8 variants require an extra channel for PCS clock routing and control. The ×8 variants use channel 4for clocking.Table 4-9: Number of Logical and

Signal Direction Descriptionrx_st_bar[7:0]Output The decoded BAR bits for the TLP. Valid for MRd, MWr, IOWR, andIORD TLPs. Ignored for the completion

Signal Direction Descriptionrx_st_sopOutput Indicates that this is the first cycle of the TLP when rx_st_validis asserted.rx_st_valid Output Clocks r

Table 4-11: Mapping Between tl_cfg_sts and Configuration Space Registerstl_cfg_sts Configuration Space Register Description[52:49] Device Status Regis

Feature Avalon‑ST Interface Avalon‑MM Interface Avalon‑MM DMAOut-of-ordercompletions(transparent to theApplication Layer)Not supported Supported Suppo

tl_cfg_sts Configuration Space Register Description[29:25] Status Register[15:11] Records the following 5 primary commandstatus errors:• Bit 15: detec

Configuration Space Register AccessThe tl_cfg_ctl signal is a multiplexed bus that contains the contents of Configuration Space registers asshown in t

Register Width Direction Descriptioncfg_slot_ctrl16 Output cfg_slot_ctrl[15:0] is the Slot Status of the PCIExpress capability structure. This registe

Register Width Direction Descriptioncfg_msi_addr64 Output cfg_msi_add[63:32] is the message signaledinterrupt (MSI) upper message address. cfg_msi_add

Register Width Direction Descriptioncfg_tcvcmap24 Output Configuration traffic class (TC)/virtual channel(VC) mapping. The Application Layer uses this

Bit(s) Field Description[6:4] multiple messageenableThis field indicates permitted values for MSI signals. For example,if “100” is written to this fie

Related InformationPin-out Files for Altera DevicesPhysical Layout of Hard IP in Arria V Devices/>Arria V devices include one or two Hard IP for PC

Figure 4-9: Arria V Transceiver Bank and Hard IP for PCI Express IP Core Locations in Arria V SX and STDevicesCh5Ch4Ch3Ch2Ch1Ch0Ch5Ch4Ch3Ch2Ch1Ch0Ch5C

For more comprehensive information about Arria V transceivers, refer to the Transceiver Banks section inthe Transceiver Architecture in Arria V Device

Table 4-16: PIPE Interface SignalsIn the following table, signals that include lane number 0 also exist for other lanes.Signal Direction Descriptiontx

Release InformationTable 1-3: Hard IP for PCI Express Release InformationItem DescriptionVersion 14.1Release Date December 2014Ordering Codes No order

Signal Direction Descriptioneidleinfersel0[2:0]Output Electrical idle entry inference mechanism selection. Thefollowing encodings are defined:• 3&apos

Signal Direction Description• 5’b10101: LOs• 5’b11001: L2.transmit.Wake• 5’b11010: Speed.Recovery• 5’b11011: Recovery.Equalization, Phase 0• 5’b11100:

Test SignalsTable 4-17: Test Interface SignalsThe test_in bus provides run-time control and monitoring of the internal state of the IP core.Signal Dir

Registers52014.12.15UG-01105_avmmSubscribeSend FeedbackCorrespondence between Configuration Space Registers and the PCIeSpecificationTable 5-1: Corres

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification0x170:0x17C Reserved N/A0x180:0x1FC Virtual channel arbit

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification0x018 Base Address 2Secondary Latency Timer, Subordinate

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification0x068 MSI-X Message Control Next Cap PtrCapability IDMSI

Type 0 Configuration Space RegistersFigure 5-1: Type 0 Configuration Space Registers - Byte Address Offsets and LayoutEndpoints store configuration da

Type 1 Configuration Space RegistersFigure 5-2: Type 1 Configuration Space Registers (Root Ports)0x00000x004Device ID31242316158700x0080x00C0x0100x014

Figure 5-4: MSI-X Capability Structure0x0680x06C0x070Message Control Next Cap PtrMSI-X Table OffsetMSI-X Pending Bit Array (PBA) Offset31 24 23 16 15

ConfigurationsThe Avalon-MM Arria V Hard IP for PCI Express includes a full hard IP implementation of the PCIExpress stack comprising the following la

Figure 5-7: PCI Express Capability Structure - Byte Address Offsets and LayoutIn the following table showing the PCI Express Capability Structure, reg

Altera-Defined VSEC RegistersFigure 5-8: VSEC RegistersThis extended capability structure supports Configuration via Protocol (CvP) programming and de

Table 5-3: Altera‑Defined Vendor Specific HeaderYou can specify these values when you instantiate the Hard IP. These registers are read-only at run-ti

Table 5-7: CvP StatusThe CvP Status register allows software to monitor the CvP status signals.Bits Register Description Reset Value Access[31:26] Res

Bits Register Description Reset Value Access[1] HIP_CLK_SEL. Selects between PMA and fabric clock when USER_MODE = 1 and PLD_CORE_READY = 1. The follo

Bits Register Description Reset Value Access[1] START_XFER. Sets the CvP output to the FPGA control blockindicating the start of a transfer.1’b0 RW[0]

The following table describes the four subregions.Table 5-11: Avalon-MM Control and Status Register Address SpacesAddressRange Address Space Usage0x00

Address Range Register0x3070 INT-X Interrupt Enable Register for Root Ports0x3070 INT-X Interrupt Enable Register for Endpoints0x3A00-0x3A1F Avalon-MM

Bit Name Access Description[15:0] AVL_IRQ_ASSERTED[15:0] RO Current value of the Avalon-MM interrupt(IRQ) input ports to the Avalon-MM RXmaster port:•

Bits Name Access Description[15:0]AVL_IRQ_VectorRO Stores the interrupt vector of the systeminterconnect fabric. The host softwareshould read this reg

PCIe LinkPCIe Hard IPRPSwitchPCIeHard IPRPUser ApplicationLogicPCIe Hard IPEPPCIe LinkPCIe LinkUser ApplicationLogicAltera FPGA with Hard IP for PCI E

Address Name Access Description0x0904 A2P_MAILBOX1 RO Avalon-MM-to-PCI Express Mailbox 10x0908 A2P_MAILBOX2 RO Avalon-MM-to-PCI Express Mailbox 20x090

Address Bits Name Access Description0x1008[1:0]A2P_ADDR_SPACE1RW Address space indication for entry 1. Refer to thefollowing encodings are defined:• 2

Bits Name Access Description1ERR_PCI_READ_FAILURERW1C When set to 1, indicates the failure of aPCI Express read. This bit can also becleared by writin

Table 5-20: INT‑X Interrupt Enable Register for Endpoints, 0x3070Bits Name Access Description[31:0]PCI Express to Avalon-MMInterrupt EnableRW When set

The PCI Express-to-Avalon-MM Mailbox registers are read-only at the addresses shown in thefollowing table. The Avalon-MM processor reads these registe

Byte OffsetRegister Dir Description14'h3C08 cfg_link_ctrl[15:0]O cfg_link_ctrl[15:0]is the primary Link Controlof the PCI Express capability stru

Byte OffsetRegister Dir Description14'h3C28 cfg_msi_addr_hi[63:32]O cfg_msi_add[63:32] is the MSI upper messageaddress.14'h3C2C cfg_io_bas[1

Byte OffsetRegister Dir Description14'h3C58 cfg_tcvcmap[23:0]O Configuration traffic class (TC)/virtual channel(VC) mapping. The Application Laye

Byte OffsetRegister Dir Description• 10011: Loopback.Exit• 10100: Hot.Reset• 10101: LOs• 11001: L2.transmit.Wake• 11010: Speed.Recovery• 11011: Recove

Figure 5-10: Layout of Data with 3 Dword HeadersHeader 1 [63:32]Cycle 1Register 1Register 0Register 1Register 0Register 1Register 0Register 1Register

Debug FeaturesDebug features allow observation and control of the Hard IP for faster debugging of system-levelproblems.Related InformationDebugging on

The TX TLP programming model scales with the data width. The Application Layer performs the samewrites for both the 64- and 128-bit interfaces. The Ap

Table 5-24: Avalon‑MM Interrupt Status Registers for Root Ports, 0x3060Bits Name AccessModeDescription[31:5] Reserved — —[4]RPRX_CPL_RECEIVEDRW1C Set

Bit Name AccessModeDescription[2]INTC_RECEIVED_ENARW When set to 1’b1, enables the assertionof CraIrq_o when the Root PortInterrupt Status register IN

Figure 5-12: Root Port TLP Data RegistersRX_TX_CNTLRP_RXCPL_REG0RP_RXCPL_REGRP_RXCPL_STATUSControlRegisterAccessSlaveAvalon-MMMaster32323232646432IRQR

Root-Port Request Registers Address Range: 0x2800-0x2018Address Bits Name Access Description0x2010[31:16] Reserved — —[15:8]RP_RXCPL_STATUSR Specifies

Bits Register Description Reset Value Access[11] Mask for RX buffer posted and completion overflow error. 1b’1 RWS[10] Reserved 1b’0 RO[9] Mask for pa

Bits Register DescriptionResetValueAccess[10] Reserved.0RO[9] When set, indicates a parity error was detected on the Configu‐ration Space to TX bus in

Bits Register Description Reset Value Access[5] Mask for configuration error detected in CvP mode. 0 RWS[4:2] Reserved. 0 RO[1] Mask for retry buffer

Reset and Clocks62014.12.15UG-01105_avmmSubscribeSend FeedbackThe pin_perst signal from the input pin of the FPGA resets the Hard IP for PCI Express I

Figure 6-1: Reset Controller Block DiagramExample Designaltpcie_dev_hip_<if>_hwtcl.valtpcied_<dev>_hwtcl.svTransceiver HardReset Logic/Sof