Altera SDI Audio IP Cores Manuel d'utilisateur télécharger pdf (Page 39)

Clock Status Register

To create a 48-kHz signal synchronous to the video clock,

you must detect whether a 1 or 1/1.001 video clock rate is

used. If you detect a 1/1.001 video clock rate, this field

returns high.

RO74.17-MHz video clock7

Channel Status RAM

Read accesses within the address range 10h to 3Fh to the

channel status RAM. This field returns the 24 bytes of

channel status for X channel starting at address 10h, and

the 24 bytes of channel status for Y channel starting at

address 28h.

WOChannel status data7:0

SDI Clocked Audio Input Registers

The following tables list the registers for the SDI Clocked Audio Input IP core.

Table 5-5: SDI Clocked Audio Input Register Map

NameBytes Offset

Channel 0 Register00h

Channel 1 Register01h

FIFO Status Register02h

FIFO Reset Register03h

Table 5-6: SDI Clocked Audio Input Registers

DescriptionAccessNameBit

Channel 0 Register

The user-defined channel number of audio channel 0.RWChannel 07:0

Channel 1 Register

The user-defined channel number of audio channel 1.RWChannel status RAM select7:0

FIFO Status Register

This sticky bit reports the overflow of the clocked audio

input FIFO.

ROActive channel7:0

FIFO Reset Register

Reserved for future use.WOUnused6:0

Resets the clocked audio FIFO.WOFIFO reset7

SDI Audio IP Registers

Altera Corporation

Send Feedback

UG-SDI-AUD

SDI Clocked Audio Input Registers

5-8

2014.06.30

1 2 ... 34 35 36 37 38 39 40 41 42 43 44 ... 48 49

Pas de commentaire

Altera SDI Audio IP Cores Manuel d'utilisateur Page 39