Altera SDI Audio IP Cores Manuel d'utilisateur télécharger pdf (Page 33)

Table 5-2: SDI Audio Embed Registers

DescriptionAccessNameBit

Audio Control Register

Enables the embedding of each audio group. When working

with HD-SDI or 3G-SDI video, this register also enables

the embedding of the audio control packet when one or

more audio groups are enabled.

The following bits correspond to the number of audio

groups you specify:

• Bit [1:0] = Audio group 1

• Bit [3:2] = Audio group 2

• Bit [5:4] = Audio group 3

• Bit [7:6] = Audio group 4

RWAudio group enable7:0

Extended Control Register

When you specify the Channel Status RAM parameter

to 2, this field selects the channel pair for the RAM

written to by registers 10h to 3Fh. If you specify the

Channel Status RAM parameter to 0 or 1, ignore this

signal.

RWChannel status RAM select2:0

Reserved for future use.—Unused3

When set to 1b, this bit ignores the audio inputs and

uses the output of the sine generator as the data for each

audio group.

RWTest sine generator enable4

This register applies only for 3G-SDI Level B standard.

Controls which link the ancillary data is embedded in.

• 00b = No data is embedded

• 01b = Data is embedded only in Link B.

• 10b = Data is embedded only in Link A (default

value).

• 11b = Data is embedded in Link A and Link B at the

same time.

When set to 11b, the IP core inserts new packets after

any existing ancillary data on Link A and in the identical

location on Link B.

If the packet distribution of existing ancillary data on

Link B differs, existing packets may be corrupted. In

these circumstances, Altera recommends you use two

separate instances of the ancillary embedder.

RWLink AB Control6:5

Reserved for future use.—Unused7

SDI Audio IP Registers

Altera Corporation

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SDI Audio Embed Registers

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Altera SDI Audio IP Cores Manuel d'utilisateur Page 33

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