Altera SDI Audio IP Cores Manuel d'utilisateur télécharger pdf (Page 38)

SD EDP Presence Register

Reports which audio extended data groups are detected in

the SD-SDI stream.

ROEDP Present3:0

Reserved for future use.—Unused7:4

Error Status Register

Counts up to 15 errors since last reset. Write 1b to any bit

of this field to reset the entire counter to zero.

RWError counter3:0

Indicates that an error has been detected in the ancillary

packet checksum. This bit stays set until cleared by writing

1b to this register.

RWAncillary CS fail4

Indicates that an error has been detected in at least one of

the parity fields:

• ancillary packet parity bit

• audio sample parity bit (for SD-SDI)

• AES sample parity bit (for HD-SDI

This bit stays set until cleared by writing 1b to this register.

RWAncillary parity fail5

Indicates that an error has been detected in the channel

status CRC. This bit stays set until cleared by writing 1b to

this register.

RWChannel status CRC fail6

Indicates that an error has been detected in the ECRC that

forms part of the HD audio data packet. This bit stays set

until cleared. To clear, write 1b to this register.

RWAudio packet ECRC fail7

FIFO Status Register

Reports the amount of data in either the audio output FIFO

or the Avalon-ST audio FIFO when the optional Avalon-

ST Audio interface is used.

ROFIFO fill level6:0

This register bit goes high if one of the following occurs

(based on the output mode used):

• underflow or overflow of the audio output FIFO

• overflow of the Avalon-ST audio FIFO

This register always goes high at the beginning, so you must

clear the audio FIFO first for the register to indicate

underflow or overflow.

RWOverflow/underflow7

Clock Status Register

Defines the frequency of the generated audio.ROOffset4:0

Reserved for future use.—Unused6:5

Altera Corporation

SDI Audio IP Registers

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SDI Audio Extract Registers

UG-SDI-AUD

2014.06.30

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Altera SDI Audio IP Cores Manuel d'utilisateur Page 38

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