Altera RapidIO MegaCore Function Manuel d'utilisateur

101 Innovation DriveSan Jose, CA 95134www.altera.com UG-MC_RIOPHY-4.1 User GuideRapidIO MegaCore FunctionDocument last updated for Altera Complete Des

1–2 Chapter 1: About This MegaCore FunctionFeaturesRapidIO MegaCore Function August 2014 Altera CorporationUser GuideNew Features in the RapidIO IP Co

4–54 Chapter 4: Functional DescriptionLogical Layer ModulesRapidIO MegaCore Function August 2014 Altera CorporationUser Guide Error Management module

Chapter 4: Functional Description 4–55Logical Layer ModulesAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideDoorbell Message Generati

4–56 Chapter 4: Functional DescriptionLogical Layer ModulesRapidIO MegaCore Function August 2014 Altera CorporationUser GuideAn outbound message that

Chapter 4: Functional Description 4–57Logical Layer ModulesAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser Guide User implementation of

4–58 Chapter 4: Functional DescriptionLogical Layer ModulesRapidIO MegaCore Function August 2014 Altera CorporationUser GuideIn cycle 0, the user logi

Chapter 4: Functional Description 4–59Logical Layer ModulesAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideBits [31:0] of the gen_rx

4–60 Chapter 4: Functional DescriptionLogical Layer ModulesRapidIO MegaCore Function August 2014 Altera CorporationUser GuideFigure 4–31 shows a respo

Chapter 4: Functional Description 4–61Error Detection and ManagementAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideError Detection

4–62 Chapter 4: Functional DescriptionError Detection and ManagementRapidIO MegaCore Function August 2014 Altera CorporationUser GuideThe RapidIO IP c

Chapter 4: Functional Description 4–63Error Detection and ManagementAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser Guide Missing respon

Chapter 1: About This MegaCore Function 1–3FeaturesAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser Guide Physical layer features 1x/2x/

4–64 Chapter 4: Functional DescriptionError Detection and ManagementRapidIO MegaCore Function August 2014 Altera CorporationUser Guide Unsolicited Re

Chapter 4: Functional Description 4–65Error Detection and ManagementAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser Guide1 These errors d

4–66 Chapter 4: Functional DescriptionError Detection and ManagementRapidIO MegaCore Function August 2014 Altera CorporationUser Guide Illegal Transa

Chapter 4: Functional Description 4–67Error Detection and ManagementAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser Guide Illegal Transa

4–68 Chapter 4: Functional DescriptionError Detection and ManagementRapidIO MegaCore Function August 2014 Altera CorporationUser Guide

August 2014 Altera Corporation RapidIO MegaCore FunctionUser Guide5. SignalsThis chapter lists the RapidIO IP core signals. Qsys allows you to export

5–2 Chapter 5: SignalsPhysical Layer SignalsRapidIO MegaCore Function August 2014 Altera CorporationUser GuideStatus Packet and Error Monitoring Signa

Chapter 5: Signals 5–3Physical Layer SignalsAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideMulticast Event SignalsTable 5–5 lists t

5–4 Chapter 5: SignalsPhysical Layer SignalsRapidIO MegaCore Function August 2014 Altera CorporationUser GuidePhysical Layer Buffer Status SignalsTran

Chapter 5: Signals 5–5Physical Layer SignalsAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser Guidephy_mgmt_clk_reset InputResets the Custo

1–4 Chapter 1: About This MegaCore FunctionDevice Family SupportRapidIO MegaCore Function August 2014 Altera CorporationUser Guide Qsys support IP f

5–6 Chapter 5: SignalsPhysical Layer SignalsRapidIO MegaCore Function August 2014 Altera CorporationUser Guidereconfig_fromgxb(2)OutputDriven to an ex

Chapter 5: Signals 5–7Physical Layer SignalsAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser Guidetx_bonding_clocks_ch3[5:0]InputTransceiv

5–8 Chapter 5: SignalsPhysical Layer SignalsRapidIO MegaCore Function August 2014 Altera CorporationUser Guidereconfig_clk_ch1InputArria 10 dynamic re

Chapter 5: Signals 5–9Physical Layer SignalsAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideIn addition to customization of the tran

5–10 Chapter 5: SignalsTransport and Logical Layer SignalsRapidIO MegaCore Function August 2014 Altera CorporationUser Guidef For more information, re

Chapter 5: Signals 5–11Transport and Logical Layer SignalsAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideThe following parameters a

5–12 Chapter 5: SignalsTransport and Logical Layer SignalsRapidIO MegaCore Function August 2014 Altera CorporationUser Guide j = ((I/O slave address

Chapter 5: Signals 5–13Transport and Logical Layer SignalsAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideAvalon-ST Pass-Through Int

5–14 Chapter 5: SignalsTransport and Logical Layer SignalsRapidIO MegaCore Function August 2014 Altera CorporationUser GuideTable 5–19 describes the A

Chapter 5: Signals 5–15Transport and Logical Layer SignalsAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideTable 5–20 describes the A

Chapter 1: About This MegaCore Function 1–5IP Core VerificationAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideIP Core VerificationB

5–16 Chapter 5: SignalsTransport and Logical Layer SignalsRapidIO MegaCore Function August 2014 Altera CorporationUser GuideError Management Extension

Chapter 5: Signals 5–17Transport and Logical Layer SignalsAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuidePacket and Error Monitorin

5–18 Chapter 5: SignalsTransport and Logical Layer SignalsRapidIO MegaCore Function August 2014 Altera CorporationUser Guide

August 2014 Altera Corporation RapidIO MegaCore FunctionUser Guide6. Software InterfaceThe RapidIO IP core supports the following sets of registers th

6–2 Chapter 6: Software InterfaceRapidIO MegaCore Function August 2014 Altera CorporationUser GuideTable 6–1 lists the access codes used to describe t

Chapter 6: Software Interface 6–3August 2014 Altera Corporation RapidIO MegaCore FunctionUser Guide0x68Host Base Device ID LockMaintenance module0x6CC

6–4 Chapter 6: Software InterfacePhysical Layer RegistersRapidIO MegaCore Function August 2014 Altera CorporationUser GuidePhysical Layer RegistersTab

Chapter 6: Software Interface 6–5Physical Layer RegistersAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser Guide0x158ERRSTATPort 0 Error an

6–6 Chapter 6: Software InterfacePhysical Layer RegistersRapidIO MegaCore Function August 2014 Altera CorporationUser GuideTable 6–7. PRTCTRL—Port Res

Chapter 6: Software Interface 6–7Physical Layer RegistersAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideTable 6–9. Port 0 Local Ack

1–6 Chapter 1: About This MegaCore FunctionPerformance and Resource UtilizationRapidIO MegaCore Function August 2014 Altera CorporationUser Guide NREA

6–8 Chapter 6: Software InterfacePhysical Layer RegistersRapidIO MegaCore Function August 2014 Altera CorporationUser GuideIN_ERR_STOP[8] ROInput port

Chapter 6: Software Interface 6–9Physical Layer RegistersAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuidePORT_ERR[2] RW1CThis bit is

6–10 Chapter 6: Software InterfacePhysical Layer RegistersRapidIO MegaCore Function August 2014 Altera CorporationUser GuideTable 6–11. Port 0 Control

Chapter 6: Software Interface 6–11Transport and Logical Layer RegistersAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideTransport and

6–12 Chapter 6: Software InterfaceTransport and Logical Layer RegistersRapidIO MegaCore Function August 2014 Altera CorporationUser GuideTable 6–13. D

Chapter 6: Software Interface 6–13Transport and Logical Layer RegistersAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideCRF_SUPPORT[5

6–14 Chapter 6: Software InterfaceTransport and Logical Layer RegistersRapidIO MegaCore Function August 2014 Altera CorporationUser GuideTable 6–18. S

Chapter 6: Software Interface 6–15Transport and Logical Layer RegistersAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideCommand and S

6–16 Chapter 6: Software InterfaceTransport and Logical Layer RegistersRapidIO MegaCore Function August 2014 Altera CorporationUser Guide Maintenance

Chapter 6: Software Interface 6–17Transport and Logical Layer RegistersAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideReceive Maint

Chapter 1: About This MegaCore Function 1–7Performance and Resource UtilizationAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser Guide Mai

6–18 Chapter 6: Software InterfaceTransport and Logical Layer RegistersRapidIO MegaCore Function August 2014 Altera CorporationUser GuideTransmit Main

Chapter 6: Software Interface 6–19Transport and Logical Layer RegistersAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideRefer to “Por

6–20 Chapter 6: Software InterfaceTransport and Logical Layer RegistersRapidIO MegaCore Function August 2014 Altera CorporationUser Guide Input/Output

Chapter 6: Software Interface 6–21Transport and Logical Layer RegistersAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideInput/Output

6–22 Chapter 6: Software InterfaceTransport and Logical Layer RegistersRapidIO MegaCore Function August 2014 Altera CorporationUser GuideInput/Output

Chapter 6: Software Interface 6–23Transport and Logical Layer RegistersAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideWRITE_OUT_OF_

6–24 Chapter 6: Software InterfaceTransport and Logical Layer RegistersRapidIO MegaCore Function August 2014 Altera CorporationUser GuideTransport Lay

Chapter 6: Software Interface 6–25Transport and Logical Layer RegistersAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser Guide MSG_REQ_TIME

6–26 Chapter 6: Software InterfaceTransport and Logical Layer RegistersRapidIO MegaCore Function August 2014 Altera CorporationUser GuideDoorbell Mess

Chapter 6: Software Interface 6–27Transport and Logical Layer RegistersAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser Guide0x00Rx Doorbe

1–8 Chapter 1: About This MegaCore FunctionPerformance and Resource UtilizationRapidIO MegaCore Function August 2014 Altera CorporationUser GuideTable

6–28 Chapter 6: Software InterfaceTransport and Logical Layer RegistersRapidIO MegaCore Function August 2014 Altera CorporationUser GuideINFORMATION (

Chapter 6: Software Interface 6–29Transport and Logical Layer RegistersAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideTable 6–65. T

6–30 Chapter 6: Software InterfaceTransport and Logical Layer RegistersRapidIO MegaCore Function August 2014 Altera CorporationUser Guide

August 2014 Altera Corporation RapidIO MegaCore FunctionUser Guide7. TestbenchesThe RapidIO IP core includes a demonstration testbench for your use. T

7–2 Chapter 7: TestbenchesRapidIO MegaCore Function August 2014 Altera CorporationUser Guide1 Your specific variation may not have all of the interfac

Chapter 7: Testbenches 7–3August 2014 Altera Corporation RapidIO MegaCore FunctionUser Guide <design_name>_avalon_bfm_master.v <design_name

7–4 Chapter 7: TestbenchesRapidIO MegaCore Function August 2014 Altera CorporationUser GuideRead and write tasks that are defined in the BFM instance,

Chapter 7: Testbenches 7–5August 2014 Altera Corporation RapidIO MegaCore FunctionUser Guide ‘WRITE —transaction type to be executed wr_address—addres

7–6 Chapter 7: TestbenchesRapidIO MegaCore Function August 2014 Altera CorporationUser Guide1 The Avalon-MM write address must map into Input/Output S

Chapter 7: Testbenches 7–7August 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideInitially, the testbench performs two single word transfer

Chapter 1: About This MegaCore Function 1–9Performance and Resource UtilizationAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideTable

7–8 Chapter 7: TestbenchesRapidIO MegaCore Function August 2014 Altera CorporationUser GuideNREAD TransactionsThe next set of transactions tested are

Chapter 7: Testbenches 7–9August 2014 Altera Corporation RapidIO MegaCore FunctionUser Guide(refer to Table 6–61 on page 6–27). It programs the payloa

7–10 Chapter 7: TestbenchesRapidIO MegaCore Function August 2014 Altera CorporationUser GuideIn the first part of this test, the bfm_drbell_master sen

Chapter 7: Testbenches 7–11August 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideThe test iterates through these operations, each time inc

7–12 Chapter 7: TestbenchesRapidIO MegaCore Function August 2014 Altera CorporationUser Guide

August 2014 Altera Corporation RapidIO MegaCore FunctionUser Guide8. Qsys Design ExampleThe design example in this chapter shows you how to use Qsys t

8–2 Chapter 8: Qsys Design ExampleCreating a New Quartus II ProjectRapidIO MegaCore Function August 2014 Altera CorporationUser GuideIn this chapter y

Chapter 8: Qsys Design Example 8–3Running QsysAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser Guide1 Click Yes, if prompted, to create a

8–4 Chapter 8: Qsys Design ExampleRunning QsysRapidIO MegaCore Function August 2014 Altera CorporationUser Guidef For more information about how to us

Chapter 8: Qsys Design Example 8–5Running QsysAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser Guided. Click the Transport and Maintenance

1–10 Chapter 1: About This MegaCore FunctionPerformance and Resource UtilizationRapidIO MegaCore Function August 2014 Altera CorporationUser GuideTabl

8–6 Chapter 8: Qsys Design ExampleRunning QsysRapidIO MegaCore Function August 2014 Altera CorporationUser GuideAfter you add the RapidIO IP core comp

Chapter 8: Qsys Design Example 8–7Running QsysAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser Guide Master I/O BFM On-Chip MemoryThe BF

8–8 Chapter 8: Qsys Design ExampleRunning QsysRapidIO MegaCore Function August 2014 Altera CorporationUser Guide5. Under Port Enables, turn on and tur

Chapter 8: Qsys Design Example 8–9Running QsysAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideConnecting Unconnected ClocksInformati

8–10 Chapter 8: Qsys Design ExampleRunning QsysRapidIO MegaCore Function August 2014 Altera CorporationUser GuideRefer to Figure 8–3 to ensure that yo

Chapter 8: Qsys Design Example 8–11Running QsysAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser Guide2. On the File menu, click Save and t

8–12 Chapter 8: Qsys Design ExampleSimulating the SystemRapidIO MegaCore Function August 2014 Altera CorporationUser Guide1 If you are prompted to sav

August 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideA. Initialization SequenceThis appendix describes the most basic initialization sequ

A–2 Appendix A: Initialization SequenceRapidIO MegaCore Function August 2014 Altera CorporationUser Guidef For more information about initializing a R

August 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideC. Porting a RapidIO Design from thePrevious Version of the SoftwareThis appendix de

Chapter 1: About This MegaCore Function 1–11Release InformationAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideTable 1–8 shows the r

C–2 Appendix C: Porting a RapidIO Design from the Previous Version of the SoftwareUpgrading a RapidIO Design to the Arria 10 Device FamilyRapidIO Mega

Appendix C: Porting a RapidIO Design from the Previous Version of the Software C–3Upgrading a RapidIO Design to the Arria 10 Device FamilyAugust 2014

C–4 Appendix C: Porting a RapidIO Design from the Previous Version of the SoftwareUpgrading a RapidIO Design to the Arria 10 Device FamilyRapidIO Mega

August 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideAdditional InformationThis chapter provides additional information about the documen

Info–2 Additional InformationDocument Revision HistoryRapidIO MegaCore Function August 2014 Altera CorporationUser GuideJune 2014 (continued)Continued

Additional Information Info–3Document Revision HistoryAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideJune 2014(continued)14.0 Upda

Info–4 Additional InformationDocument Revision HistoryRapidIO MegaCore Function August 2014 Altera CorporationUser GuideJuly 2010 10.0 Added prelimin

Additional Information Info–5How to Contact AlteraAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideHow to Contact AlteraTo locate the

Info–6 Additional InformationTypographic ConventionsRapidIO MegaCore Function August 2014 Altera CorporationUser Guideh The question mark directs you

© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logosare trademar

1–12 Chapter 1: About This MegaCore FunctionInstallation and LicensingRapidIO MegaCore Function August 2014 Altera CorporationUser GuideInstallation a

Chapter 1: About This MegaCore Function 1–13Installation and LicensingAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideOpenCore Plus

1–14 Chapter 1: About This MegaCore FunctionInstallation and LicensingRapidIO MegaCore Function August 2014 Altera CorporationUser Guide

August 2014 Altera Corporation RapidIO MegaCore FunctionUser Guide2. Getting StartedYou can customize the RapidIO IP core to support a wide variety of

2–2 Chapter 2: Getting StartedFiles Generated for Altera IP Cores (Legacy Parameter Editor)RapidIO MegaCore Function August 2014 Altera CorporationUse

Chapter 2: Getting Started 2–3Files Generated for Altera IP CoresAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideThe RapidIO IP core

2–4 Chapter 2: Getting StartedSimulating IP CoresRapidIO MegaCore Function August 2014 Altera CorporationUser GuideSimulating IP CoresThe Quartus II s

Chapter 2: Getting Started 2–5Integrating Your IP Core in Your DesignAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser Guide1. For non-Arri

2–6 Chapter 2: Getting StartedIntegrating Your IP Core in Your DesignRapidIO MegaCore Function August 2014 Altera CorporationUser GuideFor Arria V, Cy

Chapter 2: Getting Started 2–7Integrating Your IP Core in Your DesignAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideExternal Transc

August 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideContentsChapter 1. About This MegaCore FunctionFeatures . . . . . . . . . . . . . .

2–8 Chapter 2: Getting StartedSpecifying ConstraintsRapidIO MegaCore Function August 2014 Altera CorporationUser GuideSpecifying ConstraintsFor non-Ar

Chapter 2: Getting Started 2–9Compiling the Full Design and Programming the FPGAAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideTabl

2–10 Chapter 2: Getting StartedInstantiating Multiple RapidIO IP CoresRapidIO MegaCore Function August 2014 Altera CorporationUser Guide1 Before compi

Chapter 2: Getting Started 2–11Instantiating Multiple RapidIO IP CoresAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideFigure 2–3 ill

2–12 Chapter 2: Getting StartedInstantiating Multiple RapidIO IP CoresRapidIO MegaCore Function August 2014 Altera CorporationUser GuideClock and Sign

Chapter 2: Getting Started 2–13Instantiating Multiple RapidIO IP CoresAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser Guide1 After you co

2–14 Chapter 2: Getting StartedInstantiating Multiple RapidIO IP CoresRapidIO MegaCore Function August 2014 Altera CorporationUser Guide

August 2014 Altera Corporation RapidIO MegaCore FunctionUser Guide3. Parameter SettingsYou customize the RapidIO IP core by specifying parameters in t

3–2 Chapter 3: Parameter SettingsPhysical Layer SettingsRapidIO MegaCore Function August 2014 Altera CorporationUser GuideTransceiver Selection The Tr

Chapter 3: Parameter Settings 3–3Physical Layer SettingsAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideBaud Rate Baud rate defines

iv ContentsRapidIO MegaCore Function August 2014 Altera CorporationUser GuideBaud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4 Chapter 3: Parameter SettingsTransport and Maintenance SettingsRapidIO MegaCore Function August 2014 Altera CorporationUser GuideTransport and Mai

Chapter 3: Parameter Settings 3–5Transport and Maintenance SettingsAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideYou specify the i

3–6 Chapter 3: Parameter SettingsI/O and Doorbell SettingsRapidIO MegaCore Function August 2014 Altera CorporationUser GuidePort Write Tx EnablePort w

Chapter 3: Parameter Settings 3–7I/O and Doorbell SettingsAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideThis parameter is not avai

3–8 Chapter 3: Parameter SettingsCapability Registers SettingsRapidIO MegaCore Function August 2014 Altera CorporationUser GuideThis parameter is not

Chapter 3: Parameter Settings 3–9Capability Registers SettingsAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideAssembly IDAssembly ID

3–10 Chapter 3: Parameter SettingsCapability Registers SettingsRapidIO MegaCore Function August 2014 Altera CorporationUser GuideEnable Switch Support

August 2014 Altera Corporation RapidIO MegaCore FunctionUser Guide4. Functional DescriptionInterfacesThe Altera RapidIO IP core supports the following

4–2 Chapter 4: Functional DescriptionInterfacesRapidIO MegaCore Function August 2014 Altera CorporationUser GuideNo byte- or bit-order swaps occur bet

Chapter 4: Functional Description 4–3Clocking and Reset StructureAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideClocking and Reset

Contents vAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideAvalon System Clock . . . . . . . . . . . . . . . . . . . . . . . . . .

4–4 Chapter 4: Functional DescriptionClocking and Reset StructureRapidIO MegaCore Function August 2014 Altera CorporationUser Guide1 You must drive th

Chapter 4: Functional Description 4–5Clocking and Reset StructureAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser Guidef For more informat

4–6 Chapter 4: Functional DescriptionClocking and Reset StructureRapidIO MegaCore Function August 2014 Altera CorporationUser GuideFigure 4–2 is a blo

Chapter 4: Functional Description 4–7Clocking and Reset StructureAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideReset for RapidIO I

4–8 Chapter 4: Functional DescriptionClocking and Reset StructureRapidIO MegaCore Function August 2014 Altera CorporationUser GuideIn systems generate

Chapter 4: Functional Description 4–9Clocking and Reset StructureAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideIn Arria V, Cyclone

4–10 Chapter 4: Functional DescriptionPhysical LayerRapidIO MegaCore Function August 2014 Altera CorporationUser GuideRapidIO IP Core Reset BehaviorCo

Chapter 4: Functional Description 4–11Physical LayerAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser Guide Error management Clock decoup

4–12 Chapter 4: Functional DescriptionPhysical LayerRapidIO MegaCore Function August 2014 Altera CorporationUser GuideLow-level Interface ReceiverThe

Chapter 4: Functional Description 4–13Physical LayerAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideThe receiver uses the CCITT poly

vi ContentsRapidIO MegaCore Function August 2014 Altera CorporationUser GuideError Detection and Management . . . . . . . . . . . . . . . . . . . .

4–14 Chapter 4: Functional DescriptionPhysical LayerRapidIO MegaCore Function August 2014 Altera CorporationUser Guide Processes incoming control sym

Chapter 4: Functional Description 4–15Physical LayerAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideYou can specify a value of 4, 8,

4–16 Chapter 4: Functional DescriptionPhysical LayerRapidIO MegaCore Function August 2014 Altera CorporationUser Guide Control symbol error —if an em

Chapter 4: Functional Description 4–17Physical LayerAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideFigure 4–6 shows sample threshol

4–18 Chapter 4: Functional DescriptionPhysical LayerRapidIO MegaCore Function August 2014 Altera CorporationUser GuideThe transmit buffer is the main

Chapter 4: Functional Description 4–19Transport LayerAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideThe following event also causes

4–20 Chapter 4: Functional DescriptionTransport LayerRapidIO MegaCore Function August 2014 Altera CorporationUser Guide Disable Destination ID checki

Chapter 4: Functional Description 4–21Transport LayerAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuidePackets with a destination ID d

4–22 Chapter 4: Functional DescriptionLogical Layer ModulesRapidIO MegaCore Function August 2014 Altera CorporationUser GuideResponse packets of ftype

Chapter 4: Functional Description 4–23Logical Layer ModulesAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser Guide Doorbell module that tr

Contents viiAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuidePort-Write Transactions . . . . . . . . . . . . . . . . . . . . . . . .

4–24 Chapter 4: Functional DescriptionLogical Layer ModulesRapidIO MegaCore Function August 2014 Altera CorporationUser Guide1 Registers in the Doorbe

Chapter 4: Functional Description 4–25Logical Layer ModulesAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideA local host can access t

4–26 Chapter 4: Functional DescriptionLogical Layer ModulesRapidIO MegaCore Function August 2014 Altera CorporationUser GuideA remote host can access

Chapter 4: Functional Description 4–27Logical Layer ModulesAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideWhen you create your cust

4–28 Chapter 4: Functional DescriptionLogical Layer ModulesRapidIO MegaCore Function August 2014 Altera CorporationUser GuideMaintenance RegisterThe M

Chapter 4: Functional Description 4–29Logical Layer ModulesAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideFigure 4–13 shows the sig

4–30 Chapter 4: Functional DescriptionLogical Layer ModulesRapidIO MegaCore Function August 2014 Altera CorporationUser Guide config_offset is generat

Chapter 4: Functional Description 4–31Logical Layer ModulesAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser Guide For a MAINTENANCE write

4–32 Chapter 4: Functional DescriptionLogical Layer ModulesRapidIO MegaCore Function August 2014 Altera CorporationUser Guide rdsize/wrsize wdptr conf

Chapter 4: Functional Description 4–33Logical Layer ModulesAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideThe payload is written to

viii ContentsRapidIO MegaCore Function August 2014 Altera CorporationUser Guide

4–34 Chapter 4: Functional DescriptionLogical Layer ModulesRapidIO MegaCore Function August 2014 Altera CorporationUser Guide “Input/Output Avalon-MM

Chapter 4: Functional Description 4–35Logical Layer ModulesAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideInput/Output Avalon-MM Ma

4–36 Chapter 4: Functional DescriptionLogical Layer ModulesRapidIO MegaCore Function August 2014 Altera CorporationUser GuideFigure 4–18 shows a block

Chapter 4: Functional Description 4–37Logical Layer ModulesAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideFor information about the

4–38 Chapter 4: Functional DescriptionLogical Layer ModulesRapidIO MegaCore Function August 2014 Altera CorporationUser GuideTable 4–8 lists the allow

Chapter 4: Functional Description 4–39Logical Layer ModulesAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideTable 4–9 lists the allow

4–40 Chapter 4: Functional DescriptionLogical Layer ModulesRapidIO MegaCore Function August 2014 Altera CorporationUser GuideInput/Output Avalon-MM Ma

Chapter 4: Functional Description 4–41Logical Layer ModulesAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideInput/Output Avalon-MM Sl

4–42 Chapter 4: Functional DescriptionLogical Layer ModulesRapidIO MegaCore Function August 2014 Altera CorporationUser GuideAn outbound request that

Chapter 4: Functional Description 4–43Logical Layer ModulesAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser Guide The Input/Output Slave

August 2014 Altera Corporation RapidIO MegaCore FunctionUser Guide1. About This MegaCore FunctionThe RapidIO® interconnect—an open standard developed

4–44 Chapter 4: Functional DescriptionLogical Layer ModulesRapidIO MegaCore Function August 2014 Altera CorporationUser GuideLet avalon_address[31:0]

Chapter 4: Functional Description 4–45Logical Layer ModulesAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideFigure 4–22 shows the I/O

4–46 Chapter 4: Functional DescriptionLogical Layer ModulesRapidIO MegaCore Function August 2014 Altera CorporationUser GuideInput/Output Slave Transl

Chapter 4: Functional Description 4–47Logical Layer ModulesAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideFigure 4–24 shows address

4–48 Chapter 4: Functional DescriptionLogical Layer ModulesRapidIO MegaCore Function August 2014 Altera CorporationUser GuideTranslation Window 2An Av

Chapter 4: Functional Description 4–49Logical Layer ModulesAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideTable 4–12 lists the allo

4–50 Chapter 4: Functional DescriptionLogical Layer ModulesRapidIO MegaCore Function August 2014 Altera CorporationUser GuideTable 4–13 lists the allo

Chapter 4: Functional Description 4–51Logical Layer ModulesAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideTable 4–14 lists the allo

4–52 Chapter 4: Functional DescriptionLogical Layer ModulesRapidIO MegaCore Function August 2014 Altera CorporationUser GuideInput/Output Avalon-MM Sl

Chapter 4: Functional Description 4–53Logical Layer ModulesAugust 2014 Altera Corporation RapidIO MegaCore FunctionUser GuideDoorbell ModuleThe Doorbe