Altera SDI Audio IP Cores Manuel d'utilisateur Page 3
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- Table des matières
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Noté. / 5. Basé sur avis des utilisateurs
SDI Audio Embed Registers.......................................................................................................................5-1
SDI Audio Extract Registers.......................................................................................................................5-4
SDI Clocked Audio Input Registers..........................................................................................................5-8
SDI Clocked Audio Output Registers.......................................................................................................5-9
SDI Audio IP Design Example............................................................................6-1
Components of Design Example...............................................................................................................6-1
SDI Transmitter P0..........................................................................................................................6-2
SDI Duplex........................................................................................................................................6-2
Audio Extract....................................................................................................................................6-2
AES Input Module...........................................................................................................................6-2
AES Output Module........................................................................................................................6-2
Audio Embed P0/P1........................................................................................................................6-2
Video Pattern Generator P0/P1.....................................................................................................6-2
Audio Pattern Generator................................................................................................................6-2
Ancillary Data Insertion P0/P1......................................................................................................6-2
Transceiver Dynamic Reconfiguration Control Logic...............................................................6-3
Hardware and Software Requirements.....................................................................................................6-3
Running the Design Example.....................................................................................................................6-4
Transmit SD-SDI with Embedding of Audio Group 1...............................................................6-5
Transmit HD-SDI with Embedding of Audio Group 1 and 2...................................................6-5
Transmit 3G-SDI Level A with Embedding of Audio Group 1, 2 and 3..................................6-6
Transmit 3G-SDI Level B with Embedding of Audio Group 1, 2, 3 and 4..............................6-6
Additional Information......................................................................................7-1
Document Revision History.......................................................................................................................7-1
How to Contact Altera................................................................................................................................7-1
Altera Corporation
TOC-3
SDI Audio IP Cores User Guide
- SDI Audio IP Cores User Guide 1
- Contents 2
- Altera Corporation 3
- SDI Audio IP Overview 4
- • SDI II IP Core User Guide 5
- SDI Audio IP Getting Started 6
- SDI Audio Embed IP Core 10
- SDI Audio Embed Parameters 11
- DescriptionValueParameter 12
- SDI Audio Extract IP Core 13
- SDI Audio Extract Parameters 14
- Related Information 15
- AES Format 16
- Avalon-ST Audio Interface 17
- DescriptionType Identifier 18
- Simulating the Testbench 19
- Guidelines 20
- SDI Audio Embed Signals 21
- UG-SDI-AUD 22
- 2014.06.30 22
- SDI Audio Extract Signals 25
- SDI Audio IP Registers 32
- DescriptionAccessNameBit 33
- Audio Control Register 33
- Extended Control Register 33
- Video Status Register 34
- SD EDP Control Register 34
- SDI Audio Extract Registers 35
- NameBytes Offset 36
- Audio Presence Register 37
- Audio Status Register 37
- SD EDP Presence Register 38
- Error Status Register 38
- FIFO Status Register 38
- Clock Status Register 38
- Channel 0 Register00h 39
- SDI Audio IP Design Example 41
- DescriptionLED 43
- Running the Design Example 44
- D6 D7 D8 D9 D10 D11 D12 D13 45
- Additional Information 48
- • www.altera.com/support 49
- • www.altera.com/training 49
- • www.altera.com/literature 49
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