Altera POS-PHY Level 4 IP Core Manuel d'utilisateur Page 71
- Page / 142
- Table des matières
- DEPANNAGE
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide
5. Functional Description—Transmitter
The POS-PHY Level 4 IP core consists of the main SPI-4.2 processing logic, and one of
two first-in first-out (FIFO) buffer options: a single shared buffer with embedded
addressing and support for external scheduling, or an individual buffer for each port
including a full scheduler.
When the POS-PHY Level 4 IP core is configured as a transmitter, data flows from the
Atlantic
™
interface to the SPI-4.2 interface.
Features
■ Sends data packets on the SPI-4.2 interface
■ Inserts control words
■ Generates DIP-4
■ Inserts training sequence
■ Manages the FIFO buffer status
Block Description
Figure 5–1 on page 5–1 shows the blocks and clocks that comprise the transmitter IP
core.
This section describes the top-level blocks of the POS-PHY Level 4 transmitter IP core.
Figure 5–1. Block Diagram—Transmitter (Note 1) and (2)
Notes to Figure 5–1:
(1) The dotted lines illustrate the clock domain separations.
(2) These blocks and signals are only present when the individual buffers mode is selected.
Parallel-to-Serial
Converter
Scheduler
(Note 2)
Status PHY Status FSM
Status
Register
Scheduler
FIFO Buffer
User FIFO
Buffer
Data
Processor
Atlantic
Buffer 0
Atlantic
Interface 0
SPI4.2
Interface
tdclk
trefclk
txsys_cl
k
tdint_clk
rav_clk
tsclk
Atlantic
Buffer N
(Note 2)
Atlantic
Interface N
- User Guide 1
- POS-PHY Level 4 IP Core 1
- 1. About This IP Core 3
- General Description 5
- Interfaces & Protocols 6
- IP Core Verification 7
- OpenCore Plus IP Evaluation 9
- 2. Getting Started 11
- Using the Parameter Editor 12
- Upgrading Outdated IP Cores 13
- Specify Parameters 15
- Simulate the Design 17
- 3. Parameter Settings 21
- LVDS Data Rate 22
- PLL Input Frequency 23
- Data Path Width 23
- Buffer Mode 23
- Basic Parameters 24
- Atlantic FIFO Buffer Clock 25
- Atlantic Interface Width 25
- Optional Features 26
- Transmitter Options 27
- Receiver Options 28
- Starving Starving Starving 29
- Starving Hungry Hungry 29
- Starving Satisfied Satisfied 29
- FIFO RAM Blocks 30
- Note to Table 3–5: 31
- Protocol Parameters 32
- Features 39
- Block Description 39
- ALTLVDS_RX IP Core 41
- Data Processor (rx_data_proc) 42
- Atlantic Buffers 43
- Individual Buffers 44
- Status Processor 45
- Notes to Figure 4–3: 46
- Note to Table 4–1: 47
- Notes to Figure 4–4: 48
- Requirements for rxsys_clk 49
- Reset Structure 50
- Error Flagging and Handling 50
- SPI-4.2 Protocol Errors 51
- Notes to Table 4–3: 53
- DIP-4 Marking 54
- Notes to Figure 4–8: 56
- Missing SOP 59
- Missing EOP 60
- Note to Table 4–7: 62
- Note to Table 4–8: 63
- Note to Table 4–9: 63
- Latency Information 68
- Data Processor (tx_data_proc) 74
- Status Bypass Port 77
- Clock Structure 78
- Multiple Clock Domain 79
- Notes to Figure 5–4: 80
- Note to Table 5–5: 88
- 6. Testbench 99
- Variation 100
- Receiver 100
- Receiver Testbench Examples 101
- 6–4 Chapter 6: Testbench 102
- Chapter 6: Testbench 6–5 103
- 6–6 Chapter 6: Testbench 104
- Chapter 6: Testbench 6–7 105
- 6–8 Chapter 6: Testbench 106
- A. Start-Up Sequence 107
- Troubleshooting 109
- Issues and Tips—Miscellaneous 111
- Separate PLLs 113
- Shared PLL 113
- "<rx_pll>" 114
- Note to Table C–1: 115
- D. Board Design 117
- Probe Points 118
- Spare Pins 119
- JTAG Scan Chain 119
- D–4 Appendix D: Board Design 120
- Design for Testability 120
- Introduction 121
- Static Alignment 125
- Dynamic Alignment 126
- Altera Solutions 126
- Dynamic Phase Alignment (DPA) 127
- AC Timing Analysis 128
- Budgets 129
- G. Conversion from v2.2.x 131
- Receiver Signals 132
- Transmitter Signals 134
- Additional Information 139
- Note to Table: 140
- Additional Information Info–3 141
- Typographic Conventions 141
- Info–4 Additional Information 142
Produits connexes et manuels pour Instruments de mesure Altera POS-PHY Level 4 IP Core
Instruments de mesure Altera PowerPlay Early Power Estimator for Altera CPLDs Manuel d'utilisateur
(30 pages)
(30 pages)
Instruments de mesure Altera QDRII SRAM Controller MegaCore Function Manuel d'utilisateur
(68 pages)
(68 pages)
Instruments de mesure Altera SerialLite III Streaming MegaCore Function Manuel d'utilisateur
(68 pages)
(68 pages)
Instruments de mesure Altera Signal Integrity Development Kit, Stratix V GX Edi Manuel d'utilisateur
(52 pages)
(52 pages)
© 2020, manymanuals.fr. Tous droits réservés | 0.034 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Commentaires sur ces manuels