Altera POS-PHY Level 4 IP Core Manuel d'utilisateur Page 5
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Chapter 1: About This IP Core 1–3
General Description
December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide
■ Error detection and handling
■ Protocol checking—SPI-4.2 datapath state machine check and repair
■ Atlantic FIFO buffer overflow handling
■ Status framing hysteresis (good and bad thresholds)
■ DIP-4 hysteresis (good and bad thresholds)
■ IP functional simulation models for use in Altera-supported VHDL and Verilog
HDL simulators
■ I-Tested certification
General Description
The packet over SONET/SDH physical layer (POS-PHY) Level 4 interface, first
developed by the SATURN
®
Development Group, was adopted by the Optical
Internetworking Forum (OIF) as the System Packet Interface Level 4—Phase 2 (SPI-
4.2). Therefore, POS-PHY Level 4 and SPI-4.2 are synonymous.
The POS-PHY Level 4 IP core uses the SPI-4.2 interface for high-speed cell and packet
transfers between physical (PHY) and link-layer devices. The SPI-4.2 interface
supports a data width of 16 bits (LVDS solution) and can be a PHY-link, link-link, link-
PHY, or PHY-PHY connection in multi-gigabit applications, including: asynchronous
transfer mode (ATM) and packet over SONET/SDH (STS-192/STM-64), 10 Gigabit
Ethernet, and multi-channel Gigabit and Fast Ethernet.
In compliance with the SPI-4.2 interface specification, the POS-PHY Level 4 IP core
allows you to implement transmit and receive functions.
Figure 1–1 shows a full-duplex POS-PHY Level 4 IP core configured for the link layer
in an Altera FPGA device.
Figure 1–2 shows a full-duplex POS-PHY Level 4 IP core configured for the PHY layer
in an Altera FPGA device.
Figure 1–1. POS-PHY Level 4 IP Core as Link Layer Configuration
FPGA
SPI-4.2 Interface
Switch
Interface
User Packet
Processing
OC-192
POS Framer
or
10 GbitE MAC
Switch
Fabric
Atlantic Interface
POS-PHY Level 4
Receiver
POS-PHY Level 4
Transmitter
Figure 1–2. POS-PHY Level 4 IP Core as PHY Layer Configuration
OC-192 or
10 GbitE
FPGA
Framer or MAC
Logic
Packet
Classifier
SPI-4.2 InterfaceAtlantic Interface
POS-PHY Level 4
Receiver
POS-PHY Level 4
Transmitter
- User Guide 1
- POS-PHY Level 4 IP Core 1
- 1. About This IP Core 3
- General Description 5
- Interfaces & Protocols 6
- IP Core Verification 7
- OpenCore Plus IP Evaluation 9
- 2. Getting Started 11
- Using the Parameter Editor 12
- Upgrading Outdated IP Cores 13
- Specify Parameters 15
- Simulate the Design 17
- 3. Parameter Settings 21
- LVDS Data Rate 22
- PLL Input Frequency 23
- Data Path Width 23
- Buffer Mode 23
- Basic Parameters 24
- Atlantic FIFO Buffer Clock 25
- Atlantic Interface Width 25
- Optional Features 26
- Transmitter Options 27
- Receiver Options 28
- Starving Starving Starving 29
- Starving Hungry Hungry 29
- Starving Satisfied Satisfied 29
- FIFO RAM Blocks 30
- Note to Table 3–5: 31
- Protocol Parameters 32
- Features 39
- Block Description 39
- ALTLVDS_RX IP Core 41
- Data Processor (rx_data_proc) 42
- Atlantic Buffers 43
- Individual Buffers 44
- Status Processor 45
- Notes to Figure 4–3: 46
- Note to Table 4–1: 47
- Notes to Figure 4–4: 48
- Requirements for rxsys_clk 49
- Reset Structure 50
- Error Flagging and Handling 50
- SPI-4.2 Protocol Errors 51
- Notes to Table 4–3: 53
- DIP-4 Marking 54
- Notes to Figure 4–8: 56
- Missing SOP 59
- Missing EOP 60
- Note to Table 4–7: 62
- Note to Table 4–8: 63
- Note to Table 4–9: 63
- Latency Information 68
- Data Processor (tx_data_proc) 74
- Status Bypass Port 77
- Clock Structure 78
- Multiple Clock Domain 79
- Notes to Figure 5–4: 80
- Note to Table 5–5: 88
- 6. Testbench 99
- Variation 100
- Receiver 100
- Receiver Testbench Examples 101
- 6–4 Chapter 6: Testbench 102
- Chapter 6: Testbench 6–5 103
- 6–6 Chapter 6: Testbench 104
- Chapter 6: Testbench 6–7 105
- 6–8 Chapter 6: Testbench 106
- A. Start-Up Sequence 107
- Troubleshooting 109
- Issues and Tips—Miscellaneous 111
- Separate PLLs 113
- Shared PLL 113
- "<rx_pll>" 114
- Note to Table C–1: 115
- D. Board Design 117
- Probe Points 118
- Spare Pins 119
- JTAG Scan Chain 119
- D–4 Appendix D: Board Design 120
- Design for Testability 120
- Introduction 121
- Static Alignment 125
- Dynamic Alignment 126
- Altera Solutions 126
- Dynamic Phase Alignment (DPA) 127
- AC Timing Analysis 128
- Budgets 129
- G. Conversion from v2.2.x 131
- Receiver Signals 132
- Transmitter Signals 134
- Additional Information 139
- Note to Table: 140
- Additional Information Info–3 141
- Typographic Conventions 141
- Info–4 Additional Information 142
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