Altera POS-PHY Level 4 IP Core Manuel d'utilisateur Page 37
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Chapter 3: Parameter Settings 3–17
Protocol Parameters
December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide
1 FTL must be greater than zero.
This threshold is defined in terms of bytes, with a valid range from: N to
buffer size
,
in increments of N bytes, where:
■ N = 4 or 8 bytes for 32-bit data path variations
■ N = 8 or 16 bytes for 64-bit data path variations
■ N = 16 bytes for 128-bit data path variations
The N-byte values for the 32-bit and 64-bit variations depend on the Atlantic interface
width. If the Atlantic interface width is greater than the data path width, the larger
value for N is used.
For the DIP-4 good and DIP-4 bad threshold values, two 4-bit inputs are associated
with the DIP-4 OOS state machine:
good_level
(
ctl_rd_dip4_good_threshold
) and
bad_level
(
ctl_rd_dip4_bad_threshold
).
If the
stat_rd_dip4_oos
signal is high, and all of the DIP-4s in the control words
received in the current clock cycle (up to 8 in 128-bit mode) are good, the good counter
is incremented by 1; otherwise it is reset to 0. If the good counter reaches the
good_level
threshold, the
stat_rd_dip4_oos
flag is cleared. A
good_level
of 0 is
invalid.
If the
stat_rd_dip4_oos
signal is low, and all of the DIP-4s in the control words
received in the current clock cycle (up to 8 in 128-bit mode) are errored, the bad
counter is incremented by 1; otherwise it is reset to 0. If the bad counter reaches the
bad_level
threshold, the
stat_rd_dip4_oos
flag is asserted. A
bad_level
of 0 is
invalid.
1 The receiver may need to receive more control word DIP-4 errors than the DIP-4 bad
threshold parameter set in the wizard, for
stat_rd_dip4_oos
to go high.
f For more information, refer to “DIP-4 Marking” on page 4–16 and “DIP-4 Out of
Service Indication” on page 4–17.
- User Guide 1
- POS-PHY Level 4 IP Core 1
- 1. About This IP Core 3
- General Description 5
- Interfaces & Protocols 6
- IP Core Verification 7
- OpenCore Plus IP Evaluation 9
- 2. Getting Started 11
- Using the Parameter Editor 12
- Upgrading Outdated IP Cores 13
- Specify Parameters 15
- Simulate the Design 17
- 3. Parameter Settings 21
- LVDS Data Rate 22
- PLL Input Frequency 23
- Data Path Width 23
- Buffer Mode 23
- Basic Parameters 24
- Atlantic FIFO Buffer Clock 25
- Atlantic Interface Width 25
- Optional Features 26
- Transmitter Options 27
- Receiver Options 28
- Starving Starving Starving 29
- Starving Hungry Hungry 29
- Starving Satisfied Satisfied 29
- FIFO RAM Blocks 30
- Note to Table 3–5: 31
- Protocol Parameters 32
- Features 39
- Block Description 39
- ALTLVDS_RX IP Core 41
- Data Processor (rx_data_proc) 42
- Atlantic Buffers 43
- Individual Buffers 44
- Status Processor 45
- Notes to Figure 4–3: 46
- Note to Table 4–1: 47
- Notes to Figure 4–4: 48
- Requirements for rxsys_clk 49
- Reset Structure 50
- Error Flagging and Handling 50
- SPI-4.2 Protocol Errors 51
- Notes to Table 4–3: 53
- DIP-4 Marking 54
- Notes to Figure 4–8: 56
- Missing SOP 59
- Missing EOP 60
- Note to Table 4–7: 62
- Note to Table 4–8: 63
- Note to Table 4–9: 63
- Latency Information 68
- Data Processor (tx_data_proc) 74
- Status Bypass Port 77
- Clock Structure 78
- Multiple Clock Domain 79
- Notes to Figure 5–4: 80
- Note to Table 5–5: 88
- 6. Testbench 99
- Variation 100
- Receiver 100
- Receiver Testbench Examples 101
- 6–4 Chapter 6: Testbench 102
- Chapter 6: Testbench 6–5 103
- 6–6 Chapter 6: Testbench 104
- Chapter 6: Testbench 6–7 105
- 6–8 Chapter 6: Testbench 106
- A. Start-Up Sequence 107
- Troubleshooting 109
- Issues and Tips—Miscellaneous 111
- Separate PLLs 113
- Shared PLL 113
- "<rx_pll>" 114
- Note to Table C–1: 115
- D. Board Design 117
- Probe Points 118
- Spare Pins 119
- JTAG Scan Chain 119
- D–4 Appendix D: Board Design 120
- Design for Testability 120
- Introduction 121
- Static Alignment 125
- Dynamic Alignment 126
- Altera Solutions 126
- Dynamic Phase Alignment (DPA) 127
- AC Timing Analysis 128
- Budgets 129
- G. Conversion from v2.2.x 131
- Receiver Signals 132
- Transmitter Signals 134
- Additional Information 139
- Note to Table: 140
- Additional Information Info–3 141
- Typographic Conventions 141
- Info–4 Additional Information 142
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