Altera POS-PHY Level 4 IP Core Manuel d'utilisateur Page 115
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December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide
C. Optimum Frequency for rxsys_clk
The IP core’s protocol logic and all Atlantic FIFO buffers share a common clock called
rxsys_clk
that clocks both the write and read sides of the Atlantic FIFO buffers.
Table C–1 shows the
rxsys_clk
clock frequency restrictions.
Restriction (a) is imposed by the SOP alignment block, which moves the SOP for each
packet into the first-byte position. This move slows the pipeline and temporarily fills
up the alignment buffer. If the higher frequency requirement is not met, the alignment
buffer may overflow. To guarantee correct system operation, the smallest expected
packet size should be used, and the assumption that the IP core is receiving a constant
stream of packets is made.
Restriction (b) comes from the status generation. The IP core requires one clock cycle
more than the length of the status frame to generate a status frame. This cycle is added
on the
rxsys_clk
domain, thus it must be faster than
rsclk
. If this requirement is not
met, the IP core does not operate correctly,
err_ry_stat_fifo
is asserted periodically,
and the status generated is invalid. The worst case is the minimum length status
frame which is three cycles long, giving a ratio of 4/3.
For example, consider a 128-bit IP core with an LVDS data rate of 800 Mbps, using a
single port, a calendar length of 1, and a calendar multiple of 1. For this example,
rdint_clk
=
rsclk
= 100 MHz.
For a minimum packet size of 48 bytes, the required frequency for
rxsys_clk
from
restriction (a) is:
C1 = (48 +2) /16 = 3.125
Required
rxsys_clk
frequency [Ceiling (3.1251) / 3.125] × 100 = (4/3.125) × 100
= 128 MHz
The required frequency from restriction (b) is:
Status Frame Length = 3
rxsys_clk
frequency 100 × (3+1) /3 = 100 × 4/3 = 133.34 MHz
For this example,
rxsys_clk
133.34 MHz
Table C–1. rxsys_clk Frequency Restrictions
Data Path
Width (Bits)
Restriction
Label
Restriction
32 a
rxsys_clk
frequency
rdint_clk
frequency
64 a
rxsys_clk
frequency [Ceiling (C1) / C1] ×
rdint_clk
frequency
where C1 = (Packet Length +2)/8 (1)
128
a
rxsys_clk
frequency (Ceiling (C1, 1) / C1) ×
rdint_clk
frequency
where C1 = (Packet Length +2)/16 (1)
b
rxsys_clk
frequency
rsclk
× (Status Frame Length + 1)/(Status Frame Length)
Note to Table C–1:
(1) For packet lengths 16 bytes, C1 = 1.
- User Guide 1
- POS-PHY Level 4 IP Core 1
- 1. About This IP Core 3
- General Description 5
- Interfaces & Protocols 6
- IP Core Verification 7
- OpenCore Plus IP Evaluation 9
- 2. Getting Started 11
- Using the Parameter Editor 12
- Upgrading Outdated IP Cores 13
- Specify Parameters 15
- Simulate the Design 17
- 3. Parameter Settings 21
- LVDS Data Rate 22
- PLL Input Frequency 23
- Data Path Width 23
- Buffer Mode 23
- Basic Parameters 24
- Atlantic FIFO Buffer Clock 25
- Atlantic Interface Width 25
- Optional Features 26
- Transmitter Options 27
- Receiver Options 28
- Starving Starving Starving 29
- Starving Hungry Hungry 29
- Starving Satisfied Satisfied 29
- FIFO RAM Blocks 30
- Note to Table 3–5: 31
- Protocol Parameters 32
- Features 39
- Block Description 39
- ALTLVDS_RX IP Core 41
- Data Processor (rx_data_proc) 42
- Atlantic Buffers 43
- Individual Buffers 44
- Status Processor 45
- Notes to Figure 4–3: 46
- Note to Table 4–1: 47
- Notes to Figure 4–4: 48
- Requirements for rxsys_clk 49
- Reset Structure 50
- Error Flagging and Handling 50
- SPI-4.2 Protocol Errors 51
- Notes to Table 4–3: 53
- DIP-4 Marking 54
- Notes to Figure 4–8: 56
- Missing SOP 59
- Missing EOP 60
- Note to Table 4–7: 62
- Note to Table 4–8: 63
- Note to Table 4–9: 63
- Latency Information 68
- Data Processor (tx_data_proc) 74
- Status Bypass Port 77
- Clock Structure 78
- Multiple Clock Domain 79
- Notes to Figure 5–4: 80
- Note to Table 5–5: 88
- 6. Testbench 99
- Variation 100
- Receiver 100
- Receiver Testbench Examples 101
- 6–4 Chapter 6: Testbench 102
- Chapter 6: Testbench 6–5 103
- 6–6 Chapter 6: Testbench 104
- Chapter 6: Testbench 6–7 105
- 6–8 Chapter 6: Testbench 106
- A. Start-Up Sequence 107
- Troubleshooting 109
- Issues and Tips—Miscellaneous 111
- Separate PLLs 113
- Shared PLL 113
- "<rx_pll>" 114
- Note to Table C–1: 115
- D. Board Design 117
- Probe Points 118
- Spare Pins 119
- JTAG Scan Chain 119
- D–4 Appendix D: Board Design 120
- Design for Testability 120
- Introduction 121
- Static Alignment 125
- Dynamic Alignment 126
- Altera Solutions 126
- Dynamic Phase Alignment (DPA) 127
- AC Timing Analysis 128
- Budgets 129
- G. Conversion from v2.2.x 131
- Receiver Signals 132
- Transmitter Signals 134
- Additional Information 139
- Note to Table: 140
- Additional Information Info–3 141
- Typographic Conventions 141
- Info–4 Additional Information 142
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