Altera Phase-Locked Loop Reconfiguration IP Core Manuel d'utilisateur télécharger pdf (Page 49)

Specifications Page 49

Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera Corporation

Table 14 lists the

counter_type

and

counter_param

settings for Stratix and Stratix GX

devices.

Table 14. counter_type and counter_param Settings for Stratix and Stratix GX Devices (Part 1

of 2)

Counter Settings

counter_type[]

4-bit bus that selects which counter type must be updated. The following

mapping determines which counter is specified for each

counter_type

value.

counter_type[3..0]

Selected Counter

(1)

0000 (0x0)

0001 (0x1)

0010 (0x2)

0011 (0x3)

0100 (0x4)

0101 (0x5)

0110 (0x6)

0111 (0x7)

1000 (0x8)

1001 (0x9)

1010 (0xA)

1011 (0xB)

1100 (0xC)

1101 (0xD)

1110 (0xE)

1111 (0xF)

(Illegal value)

1 2 ... 44 45 46 47 48 49 50 51

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Altera Phase-Locked Loop Reconfiguration IP Core Manuel d'utilisateur Page 49