Altera Phase-Locked Loop Reconfiguration IP Core Manuel d'utilisateur télécharger pdf (Page 45)

Specifications Page 45

Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera Corporation

Table 11 lists the

counter_type

settings for Stratix III, Stratix IV, Cyclone III,

Cyclone IV, and Arria II GX devices.

scan_init_file

String No

Specifies the name of the .mif or .hex used as the initial value of the scan

chain cache. Values are <filename> and

UNUSED

. If omitted, the value for

every entry in the cache is

. You must set the input file as shown in the

following table:

Device Input File Size

Stratix series devices

(except Stratix III and Stratix IV

devices)

192 bits or 288 bits depending on

the

scan_chain

length

Stratix III and Stratix IV Top/Bottom

PLL devices

234 bits

Stratix III and Stratix IV Right/Left

PLL devices

180 bits

Cyclone III and Cyclone IV devices 144 bits

Arria II GX devices 180 bits

use_scanclk_sync_

String No

Specifies whether to use the

scanclk

port for the synchronization mode for

the register. Available for all supported devices except Stratix III, Stratix IV,

Cyclone III, Cyclone IV, HardCopy III, HardCopy IV, and Arria II GX devices.

Values are

YES

and

. If omitted, the default value is

Table 10. ALTPLL_RECONFIG Megafunction Parameters (Part 2 of 2)

Parameter Type Required? Description

Table 11. counter_type[3..0] Settings for Stratix III, Stratix IV, Cyclone III, Cyclone IV, and

Arria II GX Devices (Part 1 of 2)

Counter Selection Binary Decimal

0000 0

0001 1

CP/LF

0010 2

VCO

0011 3

(1)

0100 4

(1)

0101 5

(1)

0110 6

(1)

0111 7

(1)

1000 8

(2)

1001 9

(2)

1010 10

(3)

1011 11

(3)

1100 12

(3)

1101 13

Illegal value 1110 14

1 2 ... 40 41 42 43 44 45 46 47 48 49 50 51

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