Altera Phase-Locked Loop Reconfiguration IP Core Manuel d'utilisateur télécharger pdf (Page 11)

Design Example Page 11

Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera Corporation

6. In the MegaWizard Plug-In Manager pages, select or verify the configuration

settings listed in Table 2. Click Next to advance from one page to the next.

Table 2. Configuration Settings for the ALTPLL Megafunction (Part 1 of 2)

MegaWizard Plug-In

Manager Page

Settings Value

Megafunction Under the I/O category, select ALTPLL

Which device family will you be using? Stratix

Which type of output file do you want to

create?

VHDL

What name do you want for the output file? reconfig_pll

Return to this page for another create

operation

Turned on

Parameter Settings

(General/Modes)

Currently selected device family Stratix

Match project/default Turned on

Which device speed grade will you be

using?

Any

What is the frequency of inclk0 input 100 MHz

Which PLL type will you be using? Enhanced PLL

How will the PLL outputs be generated?

Select Use the feedback path inside the PLL.

Select In normal mode

Which output clock will be compensated

for?

Parameter Settings

(Scan/Inputs/Lock)

Create optional inputs for dynamic

reconfiguration

Turned on

Long chain: All 6 core and 4 external clocks

are available

Selected

Create an ‘pllena’ input to selectively enable

the PLL

Turned off

Create an ‘areset’ input to asynchronously

reset the PLL

Turned on

Create an ‘pfdena’ input to selectively

enable the phase/frequency detector

Turned off

Create ‘locked’ output Turned on

Create output file(s) using ‘Advanced’ PLL

parameters

Turned off

Output Clocks

(clk c0)

Use this clock Turned on

Enter output clock frequency 100 MHz

Clock phase shift 0 degrees

Clock duty cycle (%) 50

Create a clock enable input Turned off

EDA Generate netlist Turned off

1 2 ... 6 7 8 9 10 11 12 13 14 15 16 ... 50 51

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Altera Phase-Locked Loop Reconfiguration IP Core Manuel d'utilisateur Page 11

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