Altera Phase-Locked Loop Reconfiguration IP Core Manuel d'utilisateur télécharger pdf (Page 10)

Page 10 Design Example

Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera Corporation

Design Example

You can download design examples for this megafunction from the following

locations:

■ On the Documentation: Quartus II Development Software page, in the Using

Megafunctions section under I/O

■ On the Documentation: User Guides webpage, with this user guide

The designs are simulated using the ModelSim

-Altera software to generate a

waveform display of the device behavior. For more information about the ModelSim-

Altera software, refer to the ModelSim-Altera Software Support page on the Altera

website. The support page includes links to such topics as installation, usage, and

troubleshooting.

Frequency Division

This design example uses the ALTPLL_RECONFIG megafunction to change the clock

frequency of an enhanced PLL. This example demonstrates how to reconfigure the

counter using the ALTPLL_RECONFIG megafunction to vary the frequency of this

counter by changing the c value. Figure 8 shows the formula for changing the c value

for different PLL output frequencies.

This example reconfigures the output frequency of

from 100to50MHz by

changing the divide-by value from 3 to 6.

Generating the ALTPLL and ALTPLL_RECONFIG Megafunctions

To generate the ALTPLL and ALTPLL_RECONFIG megafunctions, follow these steps:

1. Open the altpll_reconfig_DesignExample_ex1.zip file and extract

pll_recon_ex1_1.1.qar.

2. In the Quartus II software, open the pll_recon_ex1_1.1.qar file and restore the

archive file into your working directory.

3. On the Tools menu, click MegaWizard Plug-In Manager. Page 1 of the

MegaWizard Plug-In Manager appears.

4. Select Create a new custom megafunction variation.

5. Click Next. Page 2a of the MegaWizard Plug-In Manager appears.

Figure 8. Frequency Division Formula

Divide-by value = c = (Fin * m)/(Fout * n)

Where:

c value = High time count = Low time count

Fin = Input frequency

m = m modulus value

n = n modulus value

Fout = Required output frequency

1 2 ... 5 6 7 8 9 10 11 12 13 14 15 ... 50 51

Pas de commentaire

Altera Phase-Locked Loop Reconfiguration IP Core Manuel d'utilisateur Page 10