Altera Phase-Locked Loop Reconfiguration IP Core Manuel d'utilisateur télécharger pdf (Page 29)

Design Example Page 29

Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera Corporation

Figure 23 shows how the whole state machine module (

control_sm

) is being

implemented in the RTL Viewer.

Figure 21 through Figure 23 show how the state machine’s control paths and data

paths are implemented. The next section describes the state machine behavior in

detail.

Simulating the Design Example

To simulate the design example using the ModelSim-Altera software, follow these

steps:

1. Unzip the altpll_reconfig_ex3_msim.zip file to any directory on your PC.

2. Browse to the folder in which you unzipped the files.

3. Open remote_update_ex2.do file in a text editor.

4. In line 1 of the altpll_reconfig_ex3_msim.do, ensure that the directory path of the

library files is correct. For example, C:/Modeltech_ae/altera/verilog/stratix

5. On the File menu, click Save.

6. Launch the ModelSim-Altera software.

7. On the File menu, click Change Directory.

8. Select the folder in which you unzipped the files.

9. Click OK.

10. On the Tools menu, click Execute Macro.

11. Select the altpll_reconfig_ex3_msim.do file and click Open. This is a script file for

the ModelSim-Altera software to automate all of the necessary settings for the

simulation.

12. Verify the results shown in the Wave window.

Figure 23. control_sm Design Implementation via the RTL Viewer

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Altera Phase-Locked Loop Reconfiguration IP Core Manuel d'utilisateur Page 29