Altera Phase-Locked Loop Reconfiguration IP Core Manuel d'utilisateur Page 21
- Page / 51
- Table des matières
- MARQUE LIVRES
- Features 1
- Common Applications 2
- Device Family Support 2
- Parameter Settings 3
- Page 4 Parameter Settings 4
- Simulation 6
- ALTPLL_RECONFIG 7
- Note to Figure 6: 9
- Design Example 10
- Design Example Page 11 11
- Page 12 Design Example 12
- Simulating the Design Example 13
- Page 14 Design Example 14
- Pulse Width Variation 15
- Page 16 Design Example 16
- Design Example Page 17 17
- Page 18 Design Example 18
- Page 20 Design Example 20
- Design Example Page 21 21
- Page 22 Design Example 22
- Design Example Page 23 23
- Page 24 Design Example 24
- Design Example Page 25 25
- Page 26 Design Example 26
- Design Example Page 27 27
- Page 28 Design Example 28
- Page 30 Design Example 30
- Design Example Page 31 31
- (4700 to 5040 ns) 32
- Note to Figure 27: 33
- Note to Figure 28: 34
- Note to Figure 29: 35
- Note to Figure 30: 35
- (41,200 to 41,450 ns) 36
- Specifications 37
- VHDL Component Declaration 38
- Specifications Page 39 39
- Ports and Parameters 40
- Specifications Page 41 41
- Page 42 Specifications 42
- Specifications Page 43 43
- Page 44 Specifications 44
- Table 11 lists the 45
- Table 12 lists the 46
- Specifications Page 47 47
- Notes to Table 13: 48
- Specifications Page 49 49
- Document Revision History 50
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