Altera External Memory PHY Interface Manuel d'utilisateur Page 63
- Page / 83
- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Chapter 3: Functional Description—ALTMEMPHY (nonAFI) 3–47
Design Considerations
© January 2010 Altera Corporation External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide
DDR2/DDR SDRAM Full-Rate Controller
The following section details the handshake read and handshake write function for
the DDR2/DDR SDRAM full-rate controller.
f For more information about the timing diagrams of a DDR2 SDRAM
High-Performance controller, refer to the Timing Diagrams chapter in the DDR and
DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide.
Handshake Mechanism Between Read Commands and Read Data
Figure 3–14 shows the read operation for a full-rate controller. The handshake
mechanism remains similar to that of the half-rate controller except for the following
differences:
1. 1T versus 2T addressing.
As the burst size is fixed at four on the memory interface, and also the address and
command datapath is based on 1T addressing, it takes two memory clock cycles to
retrieve the data from the memory for each read command, see Figure 3–14. The
first memory cycle is the read command and the second memory cycle is the NOP
command. Because of this arrangement, you see a NOP command between the
read commands.
2. Assertion of the chip select signal.
The chip select signal is asserted along with the read command because of the 1T
addressing.
- 1
- Contents 3
- 1. About this Megafunction 5
- 2. Parameter Settings 7
- Memory Settings 8
- QDR II+/QDR II SRAM 9
- Note to Table 2–3: 12
- Note to Table 2–5: 13
- Emulated Device 14
- Actual Device 14
- Figure 2–4. Preset Editor 15
- (nonAFI) 17
- PHY-to-Controller Interfaces 20
- Initialization Timing 21
- Note to Figure 3–5: 23
- ALTMEMPHY Signals 25
- Notes to Table 3–1: 26
- Note to Table 3–2: 27
- Notes to Table 3–5: 28
- Note to Table 3–6: 31
- Note to Table 3–7: 33
- Note to Table 3–8: 35
- QDR II+/QDR II SRAM Signals 36
- Note to Table 3–11: 37
- Note to Table 3–14: 39
- Note to Table 3–15: 39
- Understanding the Testbench 41
- Functional Memory Use 42
- Figure 3–6. Example Testbench 44
- Initialization Stage 45
- Write Training Data Stage 47
- Read Calibration Phase 49
- Functional Memory Use Stage 53
- Additional Debug Signals 55
- Calibration Status Interface 56
- Design Considerations 57
- Local Interface Requirements 58
- Notes to Figure 3–12: 59
- Notes to Figure 3–13: 61
- Notes to Figure 3–14: 64
- Notes to Figure 3–15: 66
- DDR2/DDR SDRAM 69
- Clock and Reset Management 71
- Stratix II GX devices use 73
- Notes to Table 4–1: 74
- Write Datapath 76
- Address and Command Datapath 77
- ), write_clk_2x (270), or 78
- Full-Rate Support 79
- Additional Information 81
- How to Contact Altera 82
- Typographic Conventions 82
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