Altera External Memory PHY Interface Manuel d'utilisateur Page 17
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
© January 2010 Altera Corporation External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide
3. Functional Description—ALTMEMPHY
(nonAFI)
This chapter describes the QDR II+/QDR II SRAM calibration process, the typical
PHY-to-Controller interfaces that are connected to the ALTMEMPHY variation and
the signal name prefixes each module uses for nonAFI variations.
1 Altera recommends that you use the AFI for new designs; only use the nonAFI for
existing designs.
QDR II+/QDR II SRAM Calibration Process
1 This section describes the calibration process for QDR II+/QDR II SRAM interfaces
only. For information about the calibration process for DDR2 and DDR SDRAM, refer
to the Calibration section in the DDR and DDR2 SDRAM High-Performance Controllers
and ALTMEMPHY IP User Guide.
The calibration process of a QDR II+/QDR II SRAM device is considerably simpler
than that of a calibration process for a DDR2/DDR SDRAM device. The calibration
process involves selecting the right phase of the resynchronization clock to capture
the read data at half rate. Figure 3–1 shows the generation of the resynchronization
clock which then clocks the HDR registers in the IOE. During calibration, the
sequencer determines whether to use the half-rate clock or the inverted half-rate clock
to capture the half-rate data.
Figure 3–1. Resynchronization Clock in QDR II+/QDR II SRAM ALTMEMPHY Megafunction
CQn
Input from
Sequencer
D
Q
D
Q
Shift Register
1/2
shifted
D
Q
DQ
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
Half-Rate Data
CQn
shifted
- 1
- Contents 3
- 1. About this Megafunction 5
- 2. Parameter Settings 7
- Memory Settings 8
- QDR II+/QDR II SRAM 9
- Note to Table 2–3: 12
- Note to Table 2–5: 13
- Emulated Device 14
- Actual Device 14
- Figure 2–4. Preset Editor 15
- (nonAFI) 17
- PHY-to-Controller Interfaces 20
- Initialization Timing 21
- Note to Figure 3–5: 23
- ALTMEMPHY Signals 25
- Notes to Table 3–1: 26
- Note to Table 3–2: 27
- Notes to Table 3–5: 28
- Note to Table 3–6: 31
- Note to Table 3–7: 33
- Note to Table 3–8: 35
- QDR II+/QDR II SRAM Signals 36
- Note to Table 3–11: 37
- Note to Table 3–14: 39
- Note to Table 3–15: 39
- Understanding the Testbench 41
- Functional Memory Use 42
- Figure 3–6. Example Testbench 44
- Initialization Stage 45
- Write Training Data Stage 47
- Read Calibration Phase 49
- Functional Memory Use Stage 53
- Additional Debug Signals 55
- Calibration Status Interface 56
- Design Considerations 57
- Local Interface Requirements 58
- Notes to Figure 3–12: 59
- Notes to Figure 3–13: 61
- Notes to Figure 3–14: 64
- Notes to Figure 3–15: 66
- DDR2/DDR SDRAM 69
- Clock and Reset Management 71
- Stratix II GX devices use 73
- Notes to Table 4–1: 74
- Write Datapath 76
- Address and Command Datapath 77
- ), write_clk_2x (270), or 78
- Full-Rate Support 79
- Additional Information 81
- How to Contact Altera 82
- Typographic Conventions 82
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