Altera External Memory PHY Interface Manuel d'utilisateur Page 27
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Noté. / 5. Basé sur avis des utilisateurs
Chapter 3: Functional Description—ALTMEMPHY (nonAFI) 3–11
ALTMEMPHY Signals
© January 2010 Altera Corporation External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide
The ports in Table 3–3 exists for all DDR2/DDR SDRAM variations.
aux_full_rate_clk output 1 A copy of the mem_clk_2x signal that you can use in
other parts of your design.
Note to Table 3–2:
(1) Refer to Figure 4–3 for the reset mechanism in Arria GX, Cyclone III, Stratix II and Stratix II GX devices.
Table 3–2. Clock and Reset Signals for DDR2/DDR SDRAM—nonAFI (Note 1) (Part 2 of 2)
Signal Name Type Width Description
Table 3–3. PLL Reconfiguration Signals for DDR2 and DDR SDRAM—nonAFI
Signal Name Type Width Description
pll_reconfig_
enable
input 1 Allows access to the PLL reconfiguration block. Hold this
signal low in normal operation. While the ALTMEMPHY is held
in reset (via the soft_reset_n signal), and the
reset_request_n signal is 1, it is safe to reconfigure the
PLL. To reconfigure the PLL, set this signal to 1 and use the
other pll_reconfig signals to access the PLL. When
finished reconfiguring, set this signal to 0, and then set the
soft_reset_n signal to 1 to bring the ALTMEMPHY out of
reset. For this signal to work, the
PLL_RECONFIG_PORTS_EN parameter must be set to
TRUE.
pll_reconfig_
write_param
input 1 For more information, refer to the Phase-Locked Loop
(ALTPLL_RECONFIG) User Guide.
pll_reconfig_read
_param
input 1 For more information, refer to the Phase-Locked Loop
(ALTPLL_RECONFIG) User Guide.
pll_reconfig input 1 For more information, refer to the Phase-Locked Loop
(ALTPLL_RECONFIG) User Guide.
pll_reconfig_
counter_type
input 4 For more information, refer to the Phase-Locked Loop
(ALTPLL_RECONFIG) User Guide.
pll_reconfig_
counter_param
input 3 For more information, refer to the Phase-Locked Loop
(ALTPLL_RECONFIG) User Guide.
pll_reconfig_data
_in
input 9 For more information, refer to the Phase-Locked Loop
(ALTPLL_RECONFIG) User Guide.
pll_reconfig_soft
_reset_en_n
input 1 The asynchronous reset input to the PLL reconfiguration
block. This reset causes a PLL reconfiguration block reset and
holds the reset if the ALTMEMPHY megafunction in reset while
the signal is low. This port only exists in the DDR2/DDR
SDRAM variation for Arria GX, Stratix II, and Stratix II GX
devices.
pll_reconfig_busy output 1 For more information, refer to the Phase-Locked Loop
(ALTPLL_RECONFIG) User Guide.
pll_reconfig_data
_out
output 9 For more information, refer to the Phase-Locked Loop
(ALTPLL_RECONFIG) User Guide.
pll_reconfig_clk output 1 Synchronous clock to use for any logic accessing the PLL
reconfiguration interface.
pll_reconfig_
reset
output 1 Resynchronized reset to use for any logic accessing the PLL
reconfiguration interface.
- 1
- Contents 3
- 1. About this Megafunction 5
- 2. Parameter Settings 7
- Memory Settings 8
- QDR II+/QDR II SRAM 9
- Note to Table 2–3: 12
- Note to Table 2–5: 13
- Emulated Device 14
- Actual Device 14
- Figure 2–4. Preset Editor 15
- (nonAFI) 17
- PHY-to-Controller Interfaces 20
- Initialization Timing 21
- Note to Figure 3–5: 23
- ALTMEMPHY Signals 25
- Notes to Table 3–1: 26
- Note to Table 3–2: 27
- Notes to Table 3–5: 28
- Note to Table 3–6: 31
- Note to Table 3–7: 33
- Note to Table 3–8: 35
- QDR II+/QDR II SRAM Signals 36
- Note to Table 3–11: 37
- Note to Table 3–14: 39
- Note to Table 3–15: 39
- Understanding the Testbench 41
- Functional Memory Use 42
- Figure 3–6. Example Testbench 44
- Initialization Stage 45
- Write Training Data Stage 47
- Read Calibration Phase 49
- Functional Memory Use Stage 53
- Additional Debug Signals 55
- Calibration Status Interface 56
- Design Considerations 57
- Local Interface Requirements 58
- Notes to Figure 3–12: 59
- Notes to Figure 3–13: 61
- Notes to Figure 3–14: 64
- Notes to Figure 3–15: 66
- DDR2/DDR SDRAM 69
- Clock and Reset Management 71
- Stratix II GX devices use 73
- Notes to Table 4–1: 74
- Write Datapath 76
- Address and Command Datapath 77
- ), write_clk_2x (270), or 78
- Full-Rate Support 79
- Additional Information 81
- How to Contact Altera 82
- Typographic Conventions 82
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