Altera External Memory PHY Interface Manuel d'utilisateur télécharger pdf (Page 38)

3–22 Chapter 3: Functional Description—ALTMEMPHY (nonAFI)

ALTMEMPHY Signals

External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide © January 2010 Altera Corporation

The ports listed in Table 3–5 only exist when you target Stratix III and Stratix IV

devices. You can leave them unconnected if you are not using user-mode calibrated

OCT. For more information about StratixIII and StratixIV ports, refer to

ALTMEMPHY Signals section in chapter 5 of the DDR and DDR2 SDRAM

High-Performance Controllers and ALTMEMPHY IP User Guide.

reset_request_n (1) output 1 Directly connected to the locked output of the PLL and is

intended for optional use either by automated tools such

as SOPC Builder or could be manually ANDed with any

other system-level signals and combined with any edge

detect logic as required and then fed back to the

global_reset_n input.

Reset request output that indicates when the PLL outputs

are not locked. Use this as a reset request input to any

system-level reset controller you may have. This signal is

always low while the PLL is locking (but not locked), and

so any reset logic using it is advised to detect a reset

request on a falling-edge rather than by level detection.

aux_half_rate_clk output 1 A copy of the phy_clk_1x signal that you can use in

other parts of your design, same as phy_clk port.

aux_full_rate_clk output 1 A copy of the mem_clk_2x signal that you can use in

other parts of your design.

Note to Table 3–2:

(1) Refer to Figure 4–3 for the reset mechanism in Arria GX, Stratix II and Stratix II GX devices.

Table 3–12. Clock and Reset Signals for QDR II+/QDR II SRAM (Part 2 of 2)

Signal Name Type Width Description

Table 3–13. User-Mode Calibrated OCT Control Signals for QDR II+/QDR II SRAM (Note 1), (2)

Signal Name Type Width Description

oct_ctl_rs_value input 14 Specifies serial termination value. Connects to the

seriesterminationcontrol bus of the ALT_OCT

megafunction. This port exists when you target Stratix IV and

Stratix III devices only.

oct_ctl_rt_value input 14 Specifies parallel termination value. Connects to the

parallelterminationcontrol bus of the ALT_OCT

megafunction. This port exists when you target Stratix IV and

Stratix III devices only.

Notes to Table 3–5:

(1) These ports are available if you want to use user-mode OCT calibration. Otherwise, they can be left unconnected.

(2) For more information on OCT, see the ALT_OCT Megafunction User Guide.

Table 3–14. Datapath Interface for QDR II+/QDR II SRAM (Note 1) (Part 1 of 2)

Signal Name Type Width Description

ctl_mem_addr_h input MEM_IF_

ROWADDR_WIDTH

Write address from the controller to the external

memory.

ctl_mem_addr_l input MEM_IF_

ROWADDR_WIDTH

Read address from the controller to the external

memory.

1 2 ... 33 34 35 36 37 38 39 40 41 42 43 ... 82 83

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