Altera ALTDQ_DQS2 Manuel d'utilisateur télécharger pdf (Page 37)

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Port name Type Width Description

config_dqs_io_ena

Input 1 An input port that controls the

enable input on the DQS I/O

configurations. Receives the

clock enable signal for the DQS

I/O configuration block.

Refer to Dynamic Reconfigura‐

tion for ALTDQ_DQS2 on

page 38

This port is supported in Arria

V, Cyclone V, and Stratix V

devices.

config_dqs_ena

Input 1 An input port that controls the

enable input on the DQS logic.

Receives the clock enable signal

for the DQS configuration

block.

Refer to Dynamic Reconfigura‐

tion for ALTDQ_DQS2 on

page 38

This port is supported in Arria

V, Cyclone V, and Stratix V

devices.

config_update

Input 1 The ALTDQ_DQS2 dynamic

configuration interface consists

of this input port.

Receives the signal to load the

bits from the serial-to-parallel

shift registers to the configura‐

tion registers.

After scanning all the bits into

the desired scan chain blocks,

the bits can be copied at once

into the configuration register

by asserting the config_update

signal for one clock cycle.

This port is supported in Arria

V, Cyclone V, and Stratix V

devices.

UG-01089

2014.12.17

ALTDQ_DQS2 Dynamic Configuration Ports

ALTDQ_DQS2 IP Core User Guide

Altera Corporation

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Altera ALTDQ_DQS2 Manuel d'utilisateur Page 37

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