Altera ALTDQ_DQS2 Manuel d'utilisateur télécharger pdf (Page 27)

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Port Name Type Width Description

output_strobe_ena

Input 2 = half-rate

1 = full-rate

The gating signal for the

output_strobe_out port.

This port is supported in Arria

V, Cyclone V, and Stratix V

devices.

oct_ena_in

Input 2 = half-rate

1 = full-rate

Controls the dynamic on-chip-

termination signal for all data

and strobe ports.

This port is supported in Arria

V, Cyclone V, and Stratix V

devices.

reset_n_core_clock_in

Input 1 Asynchronous reset used in

QDRII-like interfaces to reset the

write strobe.

This port is supported in Arria

V, Cyclone V, and Stratix V

devices.

write_strobe_clock_in

Input 1 Receives the clock signal from

the core. For example, a DQS

signal from the core. Clocks the

DDIO that generates the output

strobe signal.

This port is supported in Arria

V, Cyclone V, and Stratix V

devices.

Note: This signal is the

main full-rate input

clock when you set

the IP type to Input

for Arria V and

Cyclone V devices.

UG-01089

2014.12.17

ALTDQ_DQS2 Data Strobe Ports

ALTDQ_DQS2 IP Core User Guide

Altera Corporation

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Altera ALTDQ_DQS2 Manuel d'utilisateur Page 27

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