Altera Triple Speed Ethernet MegaCore Function Manuel d'utilisateur Page 218
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Document Revision History
ChangesVersionDate
• Added a link to the Altera website that provides the latest device support
information for Altera IP.
• Added a note in PCS/Transceiver Options on page 3-5—You must
configure the Arria 10 Transceiver ATX PLL output clock frequency to 1250.0
MHz when using the Arria 10 Transceiver Native PHY with the Triple-Speed
Ethernet IP core.
• Added MAC Error Correction Code on page 4-19 section.
• Added new support configuration for IEEE 1588v2 feature.
• Updated the tx_period and rx_period register bits in IEEE 1588v2 Feature
(Dword Offset 0xD0 – 0xD6) on page 6-16.
• Updated the timing adjustment for the IEEE 1588v2 feature PMA delay in
IEEE 1588v2 Feature PMA Delay on page 6-17.
• Revised the control interface signal names to reg_rd, reg_data_in, reg_
wr, reg_busy, and reg_addr in MAC Control Interface Signals on page
7-3.
• Added ECC status signals in ECC Status Signals on page 7-11 and ECC
Status Signals on page 7-19.
• Added Arria 10 Transceiver Native PHY signals in Arria 10 Transceiver
Native PHY Signals on page 7-18.
• Added Transceiver Native PHY signal in Transceiver Native PHY Signal
on page 7-23.
• Updated the following the signal diagrams:
• 10/100/1000 Ethernet MAC Signals
• 1000BASE-X/SGMII PCS Function Signals
• 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals
• 10/100/1000 Multiport Ethernet MAC Function without Internal FIFO
Buffers, with IEEE 1588v2, 1000BASE-X/SGMII PCS and Embedded PMA
Signals
• Added IEEE 1588v2 feature PHY path delay interface signals in IEEE 1588v2
PHY Path Delay Interface Signals on page 7-33.
• Updated the Period and AdjustPeriod register bits in ToD Clock
Configuration Register Space on page 14-5.
• Added two new conditions that the ToD synchronizer module supports in
ToD Synchronizer chapter.
• Added three new recommended sampling clock frequencies in ToD
Synchronizer chapter.
• Added a new setting of 32/63 in ToD Synchronizer Block on page 15-2.
• Updated the SYNC_MODE parameter value and description in ToD Synchro-
nizer Parameter Settings on page 15-3.
14.0June 2014
Additional Information
Altera Corporation
Send Feedback
UG-01008
Document Revision History
F-2
2014.06.30
- User Guide 1
- Contents 2
- Altera Corporation 10
- About This MegaCore Function 10
- Send Feedback 10
- High-Level Block Diagrams 10
- Figure 1-2: Multi-port MAC 11
- 10/100/1000-Mbps 12
- Ethernet MAC 12
- Optical Platform 14
- Copper Platform 14
- Release Information 18
- DescriptionItem 19
- Using the Parameter Editor 24
- Design Walkthrough 25
- Simulate the System 27
- Programming an FPGA Device 27
- Generated Files 28
- DescriptionFile Name 29
- Quartus II Pin 29
- Assignment 29
- Parameter Settings 30
- Ethernet MAC Options 31
- FIFO Options 33
- Timestamp Options 34
- PCS/Transceiver Options 34
- ParameterValueName 35
- Functional Description 37
- MAC Architecture 38
- MAC Interfaces 39
- MAC Transmit Datapath 40
- IP Payload Re-alignment 41
- Address Insertion 41
- Frame Payload Padding 41
- CRC-32 Generation 41
- Interpacket Gap Insertion 42
- MAC Receive Datapath 43
- ValueHash Code Bit 44
- Frame Type Validation 45
- Payload Pad Removal 46
- CRC Checking 46
- Length Checking 46
- Frame Writing 47
- IP Payload Alignment 47
- FIFO Buffer Thresholds 48
- Receive Thresholds 49
- Transmit Thresholds 51
- Congestion and Flow Control 52
- Magic Packets 53
- MAC Local Loopback 54
- MAC Error Correction Code 55
- MAC Reset 55
- PHY Management (MDIO) 56
- MDIO Connection 57
- MDIO Frame Format 57
- Gigabit Ethernet 58
- Programmable 10/100 Ethernet 59
- Transmit Operation 62
- Receive Operation 63
- SGMII Converter 64
- Auto-Negotiation 65
- SGMII Auto-Negotiation 66
- Ten-bit Interface 68
- PHY Loopback 69
- PHY Power-Down 69
- POWERDOWN 70
- 1000BASE-X PCS 70
- IEEE 1588v2 Features 72
- Time of Day 73
- IEEE 1588v2 Receive Datapath 74
- IEEE 1588v2 Frame Format 74
- 0..1500/9600 Octets 75
- 4 Octets 75
- CRC4 Octets 76
- 0..1500/9600 Octets Payload 76
- MAC Header 77
- UDP Header 77
- IP Header 77
- PTP Header 77
- Software Requirements 78
- Base Addresses 80
- IEEE 1588v2 Feature PMA Delay 100
- UG-01008 101
- 2014.06.30 101
- DescriptionR/WNameBit(s) 103
- DescriptionR/WNameBit 105
- 1000BASE-X 106
- Register Initialization 110
- Configuration Register Space 111
- Interface Signals 116
- Clock and Reset Signal 117
- MAC Control Interface Signals 118
- MAC Status Signals 118
- MAC Receive Interface Signals 119
- DescriptionBit 120
- DescriptionI/OName 123
- MII/GMII/RGMII Signals 124
- PHY Management Signals 125
- ECC Status Signals 126
- TBI Interface Signals 131
- Status LED Control Signals 132
- SERDES Control Signals 132
- Related Information 133
- SectionInterface Signal 135
- 1.25 Gbps Serial Interface 138
- Transceiver Native PHY Signal 138
- DescriptionWidthI/OSignal 141
- 1000BASE-X/SGMII PCS Signals 149
- PCS Control Interface Signals 150
- PCS Reset Signals 150
- SGMII Status Signals 152
- Avalon-ST Receive Interface 155
- IEEE 1588v2 Timestamp 162
- Design Considerations 163
- Configurations(1) 164
- Sharing Transceiver Quads 169
- Timing Constraints 171
- Recommended Clock Frequency 173
- 50–100CLK 174
- 1000BASE-X/SGMII PCS only 174
- 125REF_CLK 174
- 125TBI_TX_CLK 174
- 125TBI_RX_CLK 174
- Testbench 175
- Testbench Verification 176
- Testbench Configuration 177
- Test Flow 177
- Simulation Model 178
- Simulation Model Files 179
- Driver Architecture 180
- PHY Speed Bits 181
- Speed (Mbps) 181
- Using Jumbo Frames 183
- API Functions 184
- Constants 189
- DescriptionValueConstant 190
- Ethernet Frame Format 192
- Pause Frame Format 194
- Description 195
- XON_GENXOFF_GEN 195
- Simulation Parameters 196
- DefaultDescriptionParameter 197
- Test Configuration Parameters 198
- Time-of-Day (ToD) Clock 201
- ToD Clock Parameter Setting 202
- ToD Clock 203
- DescriptionR/WNameDword 205
- Adjusting ToD Clock Drift 206
- ToD Synchronizer 207
- ToD Synchronizer Block 208
- 32/6364/31516/6364/63Settings 209
- DescriptionValueName 209
- ToD Synchronizer Signals 210
- Packet Classifier 212
- Packet Classifier Signals 213
- Additional Information 217
- Document Revision History 218
- ChangesVersionDate 219
- How to Contact Altera 223
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