Altera Triple Speed Ethernet MegaCore Function Manuel d'utilisateur télécharger pdf (Page 100)

HW ResetDescriptionR/WNameDword

Offset

0x0Static timing adjustment in fractional

nanoseconds for outbound timestamps on the

receive datapath.

• Bits 0 to 15: Timing adjustment in fractional

nanoseconds.

• Bits 16 to 31: Not used.

RWrx_adjust_fns0xD4

0x0Static timing adjustment in nanoseconds for

outbound timestamps on the receive datapath.

• Bits 0 to 15: Timing adjustment in nanosec-

onds.

• Bits 16 to 23: Not used.

RWrx_adjust_ns0xD5

IEEE 1588v2 Feature PMA Delay

PMA digital and analog delay of hardware for the IEEE 1588v2 feature and the register timing adjustment.

1 UI is equivalent to 800 ps.

Table 6-8: IEEE 1588v2 Feature PMA Delay—Hardware

Timing Adjustment

DeviceDelay

RX registerTX register

26 UI53 UIStratix V or Arria V GZ

Digital 34 UI52 UIArria V GX, Arria V GT, or Arria V SoC

44 UI32 UICyclone V GX or Cyclone V SoC

1.75 ns-1.1 nsStratix V

Analog 1.75 ns-1.1 nsArria V

1.75 ns-1.1 nsCyclone V

Table 6-9: IEEE 1588v2 Feature LVDS I/O Delay—Hardware

Timing Adjustment

DeviceDelay

RX registerTX register

36 UI11 UIStratix V or Arria V GZ

Digital

36 UI11 UIArria V GX, Arria V GT, or Arria V SoC

PMA digital and analog delay of simulation model for the IEEE 1588v2 feature and the register timing

adjustment.

Altera Corporation

Configuration Register Space

Send Feedback

6-17

IEEE 1588v2 Feature PMA Delay

UG-01008

2014.06.30

1 2 ... 95 96 97 98 99 100 101 102 103 104 105 ... 222 223

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Altera Triple Speed Ethernet MegaCore Function Manuel d'utilisateur Page 100

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