Altera Triple Speed Ethernet MegaCore Function Manuel d'utilisateur Page 156
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Noté. / 5. Basé sur avis des utilisateurs
Avalon-ST Transmit Interface
Figure 7-14: Transmit Operation—MAC With Internal FIFO Buffers
ff_tx_clk
ff_tx_data[31:0]
ff_tx_sop
ff_tx_eop
ff_tx_rdy
ff_tx_wren
ff_tx_crc_fwd
ff_tx_err
ff_tx_mod[1:0]
ff_tx_septy
tx_ff_uflow
00000001 00000002 00000003 00000004 00000005 00000006
Figure 7-15: Transmit Operation—MAC Without Internal FIFO Buffers
mac_tx_clk_0
data_tx_data_0[7:0]
data_tx_sop_0
data_tx_eop_0
data_tx_ready_0
data_tx_err_0
data_tx_valid_0
0000 01 01 01 02 03 04 05 06 07 08 09
GMII Transmit
On transmit, all data transfers are synchronous to the rising edge of tx_clk. The GMII data enable signal
gm_tx_en is asserted to indicate the start of a new frame and remains asserted until the last byte of the frame
is present on gm_tx_d[7:0] bus. Between frames, gm_tx_en remains deasserted.
If a frame is received on the Avalon-ST interface with an error (asserted with ff_tx_eop), the frame is
subsequently transmitted with the GMII gm_tx_err error signal at any time during the frame transfer.
GMII Receive
On receive, all signals are sampled on the rising edge of rx_clk. The GMII data enable signal gm_rx_dv is
asserted by the PHY to indicate the start of a new frame and remains asserted until the last byte of the frame
is present on the gm_rx_d[7:0] bus. Between frames, gm_rx_dv remains deasserted.
If the PHY detects an error on the frame received from the line, the PHY asserts the GMII error signal,
gm_rx_err, for at least one clock cycle at any time during the frame transfer.
A frame received on the GMII interface with a PHY error indication is subsequently transferred on the
Avalon-ST interface with the error signal rx_err[0] asserted.
Altera Corporation
Interface Signals
Send Feedback
7-41
Avalon-ST Transmit Interface
UG-01008
2014.06.30
- User Guide 1
- Contents 2
- Altera Corporation 10
- About This MegaCore Function 10
- Send Feedback 10
- High-Level Block Diagrams 10
- Figure 1-2: Multi-port MAC 11
- 10/100/1000-Mbps 12
- Ethernet MAC 12
- Optical Platform 14
- Copper Platform 14
- Release Information 18
- DescriptionItem 19
- Using the Parameter Editor 24
- Design Walkthrough 25
- Simulate the System 27
- Programming an FPGA Device 27
- Generated Files 28
- DescriptionFile Name 29
- Quartus II Pin 29
- Assignment 29
- Parameter Settings 30
- Ethernet MAC Options 31
- FIFO Options 33
- Timestamp Options 34
- PCS/Transceiver Options 34
- ParameterValueName 35
- Functional Description 37
- MAC Architecture 38
- MAC Interfaces 39
- MAC Transmit Datapath 40
- IP Payload Re-alignment 41
- Address Insertion 41
- Frame Payload Padding 41
- CRC-32 Generation 41
- Interpacket Gap Insertion 42
- MAC Receive Datapath 43
- ValueHash Code Bit 44
- Frame Type Validation 45
- Payload Pad Removal 46
- CRC Checking 46
- Length Checking 46
- Frame Writing 47
- IP Payload Alignment 47
- FIFO Buffer Thresholds 48
- Receive Thresholds 49
- Transmit Thresholds 51
- Congestion and Flow Control 52
- Magic Packets 53
- MAC Local Loopback 54
- MAC Error Correction Code 55
- MAC Reset 55
- PHY Management (MDIO) 56
- MDIO Connection 57
- MDIO Frame Format 57
- Gigabit Ethernet 58
- Programmable 10/100 Ethernet 59
- Transmit Operation 62
- Receive Operation 63
- SGMII Converter 64
- Auto-Negotiation 65
- SGMII Auto-Negotiation 66
- Ten-bit Interface 68
- PHY Loopback 69
- PHY Power-Down 69
- POWERDOWN 70
- 1000BASE-X PCS 70
- IEEE 1588v2 Features 72
- Time of Day 73
- IEEE 1588v2 Receive Datapath 74
- IEEE 1588v2 Frame Format 74
- 0..1500/9600 Octets 75
- 4 Octets 75
- CRC4 Octets 76
- 0..1500/9600 Octets Payload 76
- MAC Header 77
- UDP Header 77
- IP Header 77
- PTP Header 77
- Software Requirements 78
- Base Addresses 80
- IEEE 1588v2 Feature PMA Delay 100
- UG-01008 101
- 2014.06.30 101
- DescriptionR/WNameBit(s) 103
- DescriptionR/WNameBit 105
- 1000BASE-X 106
- Register Initialization 110
- Configuration Register Space 111
- Interface Signals 116
- Clock and Reset Signal 117
- MAC Control Interface Signals 118
- MAC Status Signals 118
- MAC Receive Interface Signals 119
- DescriptionBit 120
- DescriptionI/OName 123
- MII/GMII/RGMII Signals 124
- PHY Management Signals 125
- ECC Status Signals 126
- TBI Interface Signals 131
- Status LED Control Signals 132
- SERDES Control Signals 132
- Related Information 133
- SectionInterface Signal 135
- 1.25 Gbps Serial Interface 138
- Transceiver Native PHY Signal 138
- DescriptionWidthI/OSignal 141
- 1000BASE-X/SGMII PCS Signals 149
- PCS Control Interface Signals 150
- PCS Reset Signals 150
- SGMII Status Signals 152
- Avalon-ST Receive Interface 155
- IEEE 1588v2 Timestamp 162
- Design Considerations 163
- Configurations(1) 164
- Sharing Transceiver Quads 169
- Timing Constraints 171
- Recommended Clock Frequency 173
- 50–100CLK 174
- 1000BASE-X/SGMII PCS only 174
- 125REF_CLK 174
- 125TBI_TX_CLK 174
- 125TBI_RX_CLK 174
- Testbench 175
- Testbench Verification 176
- Testbench Configuration 177
- Test Flow 177
- Simulation Model 178
- Simulation Model Files 179
- Driver Architecture 180
- PHY Speed Bits 181
- Speed (Mbps) 181
- Using Jumbo Frames 183
- API Functions 184
- Constants 189
- DescriptionValueConstant 190
- Ethernet Frame Format 192
- Pause Frame Format 194
- Description 195
- XON_GENXOFF_GEN 195
- Simulation Parameters 196
- DefaultDescriptionParameter 197
- Test Configuration Parameters 198
- Time-of-Day (ToD) Clock 201
- ToD Clock Parameter Setting 202
- ToD Clock 203
- DescriptionR/WNameDword 205
- Adjusting ToD Clock Drift 206
- ToD Synchronizer 207
- ToD Synchronizer Block 208
- 32/6364/31516/6364/63Settings 209
- DescriptionValueName 209
- ToD Synchronizer Signals 210
- Packet Classifier 212
- Packet Classifier Signals 213
- Additional Information 217
- Document Revision History 218
- ChangesVersionDate 219
- How to Contact Altera 223
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