Altera MAX 10 Embedded Memory Manuel d'utilisateur télécharger pdf (Page 30)

Figure 5-2: RAM: 2-Port IP Core Signals with the One Read Port and One Write Port, and Dual Clock: Use

Separate 'Read' and 'Write' Clocks Options Enabled

data[]

wren

rdaddress[]

wr_addressstall

wrclock

wrclocken

rdclock

rdinclocken

q[]

rd_aclr

wraddress[]

rden

rd_addressstall

rdoutclocken

byteena_a[]

rdclocken

Figure 5-3: RAM: 2-Port IP Core Signals with the One Read Port and One Write Port, and Dual Clock: Use

Separate 'Input' and 'Output' Clocks Options Enabled

data[]

wren

rdaddress[]

rden

wr_addressstall

inclock

inclocken

outclock

outclocken

q[]

in_aclr

out_aclr

wraddress[]

byteena_a[]

rd_addressstall

5-2

RAM: 2-PORT IP Core References

UG-M10MEMORY

2015.05.04

Altera Corporation

RAM: 2-PORT IP Core References

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1 2 ... 25 26 27 28 29 30 31 32 33 34 35 ... 70 71

101 Innovation Drive 1
San Jose, CA 95134 1
Contents 2
Subscribe 4
Features 5
Parity Bit 6
Read Enable 6
Read-During-Write 7
Byte Enable 7
Packed Mode Support 8
Address Clock Enable Support 9
Asynchronous Clear 10
Related Information 11
Altera Corporation 12
Send Feedback 12
UG-M10MEMORY 13
2015.05.04 13
Port Width Configurations 14
Read Port 16
Write Port 16
Memory Block Valid Range 16
MAX 10 Embedded Memory Design 17
Consideration 17
A B C D E F 18
A B C D E 18
If You... ...Then 20
Signal Required Description 24
Parameter Values Description 25
Options Enabled 29
Option Enabled 53
Option Values Description 61
FIFO IP Core References 62
LPM_WIDTHU 66
ALTMEMMULT IP Core References 69
Memory User Guide 71

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Altera MAX 10 Embedded Memory Manuel d'utilisateur Page 30

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