Altera DDR SDRAM High-Performance Controllers and ALTMEMP manuels

Manuels d'utilisation et guides de l'utilisateur pour Instruments de mesure Altera DDR SDRAM High-Performance Controllers and ALTMEMP.
Nous fournissons des manuels en pdf 1 Altera DDR SDRAM High-Performance Controllers and ALTMEMP à télécharger gratuitement par type de document : Manuel d'utilisateur


Table des matières

ALTMEMPHY IP User Guide

1

Contents

3

Chapter 7. Latency

5

Chapter 8. Timing Diagrams

5

1. About This IP

7

Release Information

8

Device Family Support

8

Features

9

Unsupported Features

10

MegaCore Verification

10

Resource Utilization

11

System Requirements

12

Installation and Licensing

13

1–8 Chapter 1: About This IP

14

2. Getting Started

15

SOPC Builder Flow

16

Qsys Flow

18

Completing the Qsys System

19

Specifying Parameters

20

HardCopy Guidelines

21

Generated Files

22

3. Parameter Settings

27

Memory Settings

28

ALTMEMPHY Parameter Settings

29

Note to Table 3–3:

32

Note to Table 3–5:

34

PHY Settings

36

Board Settings

38

■ Memory Settings

39

■ PHY Settings

39

■ Board Settings

39

■ Controller Settings

39

Controller Settings

40

4. Compiling and Simulating

43

Compiling the Design

44

Simulating the Design

46

Block Description

48

Calibration

49

Address and Command Datapath

49

), or the inverted

50

Clock and Reset Management

51

Notes to Table 5–4:

54

Note to Table 5–2:

57

Cyclone III Devices

59

Read Datapath

66

Note to Figure 5–6:

68

Note to Figure 5–8:

70

Devices

71

GX Devices

72

ALTMEMPHY Signals

73

Notes to Table 5–5:

74

Note to Table 5–5:

77

Notes to Table 5–7:

79

PHY-to-Controller Interfaces

80

Altera Device

81

-- a --b

82

Figure 5–15. Full-Rate Reads

83

Figure 5–16. Half-Rate Reads

83

Notes to Figure 5–17:

85

Notes to Figure 5–18:

86

Notes to Figure 5–19:

87

Notes to Figure 5–20:

88

Preliminary Steps

89

Design Considerations

89

Clocks and Resets

89

Using a Custom Controller

90

Partial Write Operations

92

6. Functional Description—

95

Avalon-ST Input Interface

96

Command Generator

96

Timing Bank Pool

96

Arbitration Rules

97

CSR Interface

98

Data Reordering

98

Pre-emptive Bank Management

98

Quasi-1T and Quasi-2T

98

User Autoprecharge Commands

98

User-Controlled Self-Refresh

99

DDR2 SDRAM

100

Partial Writes

101

Partial Bursts

102

External Interfaces

103

Memory Side-Band Signals

104

Top-Level Signals Description

105

■ Full rate controllers

107

■ Half rate controllers

107

Sequence of Operations

111

Read Command

112

Read-Modify-Write Command

112

Example Top-Level File

113

Example Driver

114

Register Maps

116

Controller Register Map

118

7. Latency

123

7–2 Chapter 7: Latency

124

Note to Table 7–2:

125

SDRAM values

126

Handbook

127

7–6 Chapter 7: Latency

128

8. Timing Diagrams

129

Half-Rate Read

130

Half-Rate Write

132

Full-Rate Read

134

Full-Rate Write

136

Additional Information

139

Typographic Conventions

140





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