Altera DDR SDRAM High-Performance Controllers and ALTMEMP Manuel d'utilisateur Page 97
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Chapter 6: Functional Description—High-Performance Controller II 6–3
Memory Controller Architecture
June 2011 Altera Corporation External Memory Interface Handbook Volume 3
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Arbiter
The arbiter determines the order in which requests are passed to the memory device.
When the arbiter receives a single request, that request is passed immediately;
however, when multiple requests are received, the arbiter uses arbitration rules to
determine the order in which to pass requests to the memory device.
Arbitration Rules
The arbiter follows the following arbitration rules:
■ If only one master is issuing a request, grant that request immediately.
■ If there are outstanding requests from two or more masters, the arbiter applies the
following tests, in order:
a. Is there a read request? If so, the arbiter grants the read request ahead of any
write requests.
b. If neither of the above conditions apply, the arbiter grants the oldest request
first.
Rank Timer
The rank timer maintains rank-specific timing information, and performs the
following functions:
■ Ensures that only four activates occur within a specified timing window.
■ Manages the read-to-write and write-to-read bus turnaround time.
■ Manages the time-to-activate delay between different banks.
Read Data Buffer
The read data buffer receives data from the PHY and passes that data through the
input interface to the master.
Write Data Buffer
The write data buffer receives write data from the input interface and passes that data
to the PHY, upon approval of the write request.
ECC Block
The error-correcting code (ECC) block comprises an encoder and a decoder-corrector,
which can detect and correct single-bit errors, and detect double-bit errors. The ECC
block can remedy errors resulting from noise or other impairments during data
transmission.
AFI Interface
The AFI interface provides communication with the memory device, through the
physical layer logic (PHY).
For more information about AFI signals, refer to “AFI Signals” on page 5–28.
- ALTMEMPHY IP User Guide 1
- Contents 3
- Chapter 7. Latency 5
- Chapter 8. Timing Diagrams 5
- 1. About This IP 7
- Release Information 8
- Device Family Support 8
- Features 9
- Unsupported Features 10
- MegaCore Verification 10
- Resource Utilization 11
- System Requirements 12
- Installation and Licensing 13
- 1–8 Chapter 1: About This IP 14
- 2. Getting Started 15
- SOPC Builder Flow 16
- Qsys Flow 18
- Completing the Qsys System 19
- Specifying Parameters 20
- HardCopy Guidelines 21
- Generated Files 22
- 3. Parameter Settings 27
- Memory Settings 28
- ALTMEMPHY Parameter Settings 29
- Note to Table 3–3: 32
- Note to Table 3–5: 34
- PHY Settings 36
- Board Settings 38
- ■ Memory Settings 39
- ■ PHY Settings 39
- ■ Board Settings 39
- ■ Controller Settings 39
- Controller Settings 40
- 4. Compiling and Simulating 43
- Compiling the Design 44
- Simulating the Design 46
- Block Description 48
- Calibration 49
- Address and Command Datapath 49
- ), or the inverted 50
- Clock and Reset Management 51
- Notes to Table 5–4: 54
- Note to Table 5–2: 57
- Cyclone III Devices 59
- Read Datapath 66
- Note to Figure 5–6: 68
- Note to Figure 5–8: 70
- Devices 71
- GX Devices 72
- ALTMEMPHY Signals 73
- Notes to Table 5–5: 74
- Note to Table 5–5: 77
- Notes to Table 5–7: 79
- PHY-to-Controller Interfaces 80
- Altera Device 81
- -- a --b 82
- Figure 5–15. Full-Rate Reads 83
- Figure 5–16. Half-Rate Reads 83
- Notes to Figure 5–17: 85
- Notes to Figure 5–18: 86
- Notes to Figure 5–19: 87
- Notes to Figure 5–20: 88
- Preliminary Steps 89
- Design Considerations 89
- Clocks and Resets 89
- Using a Custom Controller 90
- Partial Write Operations 92
- 6. Functional Description— 95
- Avalon-ST Input Interface 96
- Command Generator 96
- Timing Bank Pool 96
- Arbitration Rules 97
- CSR Interface 98
- Data Reordering 98
- Pre-emptive Bank Management 98
- Quasi-1T and Quasi-2T 98
- User Autoprecharge Commands 98
- User-Controlled Self-Refresh 99
- DDR2 SDRAM 100
- Partial Writes 101
- Partial Bursts 102
- External Interfaces 103
- Memory Side-Band Signals 104
- Top-Level Signals Description 105
- ■ Full rate controllers 107
- ■ Half rate controllers 107
- Sequence of Operations 111
- Read Command 112
- Read-Modify-Write Command 112
- Example Top-Level File 113
- Example Driver 114
- Register Maps 116
- Controller Register Map 118
- 7. Latency 123
- 7–2 Chapter 7: Latency 124
- Note to Table 7–2: 125
- SDRAM values 126
- Handbook 127
- 7–6 Chapter 7: Latency 128
- 8. Timing Diagrams 129
- Half-Rate Read 130
- Half-Rate Write 132
- Full-Rate Read 134
- Full-Rate Write 136
- Additional Information 139
- Typographic Conventions 140
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