Altera PHY IP Core Guide de l'utilisateur Page 85
- Page / 176
- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Chapter 5: Functional Description—ALTMEMPHY 5–33
PHY-to-Controller Interfaces
December 2010 Altera Corporation External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
■ With the AFI, high and low signals are combined in one signal, so for a single chip
select (
ctl_cs_n
) interface,
ctl_cs_n[1:0]
, where location 0 appears on the
memory bus on one
mem_clk
cycle and location 1 on the next
mem_clk
cycle.
1 This convention is maintained for all signals so for an 8 bit memory
interface, the write data (
ctl_wdata
) signal is
ctl_wdata[31:0]
, where the
first data on the DQ pins is
ctl_wdata[7:0]
, then
ctl_wdata[15:8]
, then
ctl_wdata[23:16]
, then
ctl_wdata[31:24]
.
■ Word-aligned and word-unaligned reads and writes have the following
definitions:
■ Word-aligned for the single chip select is active (low) in location 1 (
_l
).
ctl_cs_n[1:0]
=
01
when a write occurs. This alignment is the easiest
alignment to design with.
■ Word-unaligned is the opposite, so
ctl_cs_n[1:0]
=
10
when a read or write
occurs and the other control and data signals are distributed across consecutive
ctl_clk
cycles.
1 The Altera high-performance controllers use word-aligned data only.
1 The timing analysis script does not support word-unaligned reads and
writes.
1 Word-unaligned reads and writes are only supported on Stratix III and
Stratix IV devices.
■ Spaced reads and writes have the following definitions:
■ Spaced writes—write commands separated by a gap of one controller clock
(
ctl_clk
) cycle
■ Spaced reads—read commands separated by a gap of one controller clock
(
ctl_clk
) cycle
Figure 5–17 through Figure 5–20 assume the following general points:
■ The burst length is four. A DDR2 SDRAM is used—the interface timing is identical
for DDR3 devices.
■ An 8-bit interface with one chip select.
■ The data for one controller clock (
ctl_clk
) cycle represents data for two memory
clock (
mem_clk
) cycles (half-rate interface).
- User Guide 1
- Contents 3
- Chapter 8. Latency 5
- Chapter 9. Timing Diagrams 5
- 1. About This IP 7
- Release Information 8
- Device Family Support 8
- 1–4 Chapter 1: About This IP 10
- Features 10
- ALTMEMPHY Megafunction 11
- Note to Table 1–4: 12
- Note to Table 1–5: 12
- High-Performance Controller 13
- System Requirements 14
- Installation and Licensing 14
- Free Evaluation 15
- 1–10 Chapter 1: About This IP 16
- 2. Getting Started 17
- Specifying Parameters 18
- SOPC Builder Flow 19
- Generated Files 22
- 3. Parameter Settings 29
- Memory Settings 30
- ALTMEMPHY Parameter Settings 31
- Note to Table 3–3: 34
- Note to Table 3–5: 38
- PHY Settings 39
- Board Settings 41
- Controller Settings 42
- 4. Compiling and Simulating 47
- Compiling the Design 48
- Simulating the Design 50
- Calibration 55
- DDR3 SDRAM Without Leveling 55
- Step 6: Postamble 57
- Step 7: Prepare for User Mode 57
- DDR3 SDRAM With Leveling 59
- Step 2: Write Leveling 62
- Address and Command Datapath 63
- ° ), or the inverted 64
- Clock and Reset Management 65
- Clock Management 65
- Note to Table 5–1: 67
- Reset Management 69
- Read Datapath 70
- Write Datapath 74
- ALTMEMPHY Signals 75
- Notes to Table 5–3: 77
- Note to Table 5–3: 79
- Notes to Table 5–5: 82
- PHY-to-Controller Interfaces 83
- Notes to Figure 5–17: 86
- Notes to Figure 5–18: 87
- Notes to Figure 5–19: 88
- Notes to Figure 5–20: 89
- Preliminary Steps 90
- Design Considerations 90
- Clocks and Resets 90
- Using a Custom Controller 91
- 6. Functional Description— 95
- Command FIFO Buffer 96
- PHY Interface Logic 98
- Control Logic 99
- Figure 6–3. ECC Block Diagram 100
- Block Description 101
- Interrupts 102
- Partial Writes 102
- Partial Bursts 103
- ECC Latency 103
- ECC Registers 104
- ECC Register Bits 106
- Example Top-Level File 108
- Example Driver 109
- Top-level Signals Description 110
- or vhd file 111
- Note to Table 6–14: 114
- 7. Functional Description— 117
- Write Data FIFO Buffer 120
- Command Queue 120
- Bank Management Logic 120
- Timer Logic 121
- Command-Issuing State Machine 121
- ODT Generation Logic 122
- User-Refresh Commands 122
- Multi-Cast Write 122
- Low-Power Mode Logic 123
- Error Correction Coding (ECC) 123
- Notes to Table 7–7: 133
- Register Maps Description 134
- ALTMEMPHY Register Map 135
- Controller Register Map 137
- 8. Latency 143
- 8–2 Chapter 8: Latency 144
- Chapter 8: Latency 8–3 145
- 8–4 Chapter 8: Latency 146
- 9. Timing Diagrams 147
- Auto-Precharge 148
- [1] [2] [3] 148
- User Refresh 149
- Initialization Timing 156
- Calibration Timing 158
- AABBCCDD AABBCCDD AABBCCDD 162
- EEFF0011 EEFF0011 EEFF0011 162
- [1] [3] [4][2] 166
- Half-Rate Read With Gaps 168
- Half-Rate Write With Gaps 169
- [2][1] [5] [4] [6][3] 170
- [12][6][7][10] [11] 172
- Additional Information 175
- Typographic Conventions 176
Oyen-digital U32 SHADOW USB 3.0 HARD DRIVE (MAC VERSION) manuels
Manuels d'utilisation et guides de l'utilisateur pour Stockage Oyen-digital U32 SHADOW USB 3.0 HARD DRIVE (MAC VERSION).
Nous fournissons des manuels en pdf 1 Oyen-digital U32 SHADOW USB 3.0 HARD DRIVE (MAC VERSION) à télécharger gratuitement par type de document : Manuel de l'utilisateur
Oyen digital U32 SHADOW USB 3.0 HARD DRIVE (MAC VERSION) Manuel de l'utilisateur (1 pages)
marque: Oyen-digital | Catégorie: Storage | Taille: 0.11 MB |
Table des matières
Plus de produits et de manuels pour Stockage Oyen-digital
| Modèles | Type de document |
|---|---|
| MINIPRO 2.5" HARD DRIVE SERIES |
Manuel de l'utilisateur
Oyen Digital MINIPRO 2.5" HARD DRIVE SERIES User Manual,
1 pages
|
| MINIPRO 2.5" ENCLOSURE SERIES |
Manuel de l'utilisateur
Oyen Digital MINIPRO 2.5" ENCLOSURE SERIES User Manual,
1 pages
|
| MINIPRO RAID SERIES |
Manuel de l'utilisateur
Oyen Digital MINIPRO RAID SERIES User Manual,
1 pages
|
| MOBIUS RAID SYSTEM |
Manuel de l'utilisateur
Oyen Digital MOBIUS RAID SYSTEM User Manual,
2 pages
|
| DATATALE RS-M2QJ 2-BAY RAID |
Manuel de l'utilisateur
Oyen Digital DATATALE RS-M2QJ 2-BAY RAID User Manual,
47 pages
|
| DATATALE RS-M4T 4-BAY THUNDERBOLT |
Manuel de l'utilisateur
Oyen Digital DATATALE RS-M4T 4-BAY THUNDERBOLT User Manual,
55 pages
|
| DATATALE RC-M4QJ 4-BAY RAID |
Manuel de l'utilisateur
Oyen Digital DATATALE RC-M4QJ 4-BAY RAID User Manual,
79 pages
|
© 2020, manymanuals.fr. Tous droits réservés | 0.026 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Commentaires sur ces manuels