Altera PHY IP Core Guide de l'utilisateur télécharger pdf (Page 54)

5–2 Chapter 5: Functional Description—ALTMEMPHY

Block Description

External Memory Interface Handbook Volume 3 December 2010 Altera Corporation

Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide

Block Description

Figure 5–1 on page 5–2 shows the major blocks of the ALTMEMPHY megafunction

and how it interfaces with the external memory device and the controller. The

ALTPLL megafunction is instantiated inside the ALTMEMPHY megafunction, so that

you do not need to generate the clock to any of the ALTMEMPHY blocks.

The ALTMEMPHY megafunction comprises the following blocks:

■ Write datapath

■ Address and command datapath

■ Clock and reset management, including DLL and PLL

■ Sequencer for calibration

■ Read datapath

Figure 5–1. ALTMEMPHY Megafunction Interfacing with the Controller and the External Memory

External

Memory

Device

ALTMEMPHY

Write

Datapath

Address

and

Command

Datapath

Clock

and Reset

Management

Sequencer

Read

Datapath

Memory

Controller

User

Logic

PLL

FPGA

DLL

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Altera PHY IP Core Guide de l'utilisateur Page 54