Altera PHY IP Core Guide de l'utilisateur Page 124
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
7–8 Chapter 7: Functional Description—High-Performance Controller II
Block Description
External Memory Interface Handbook Volume 3 December 2010 Altera Corporation
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
■ A latency increase of one clock for both writes and reads.
■ Detects and corrects all single-bit errors.
■ Detects all double-bit errors.
■ Counts the number of single-bit and double-bit errors.
■ Accepts partial writes, which trigger a read-modify-write cycle, for memory
devices with DM pins.
■ Is able to inject single-bit and double-bit errors to trigger ECC correction for
testing and debugging purposes.
■ Generates an interrupt signal when an error occurs.
When a single-bit or double-bit error occurs, the ECC logic triggers the
ecc_interrupt
signal to inform you that an ECC error has occurred. When a single-bit error occurs,
the ECC logic issues an internal read to the error address, and performs an internal
write to write back the corrected data. When a double-bit error occurs, the ECC logic
does not do any error correction but it asserts the
local_rdata_error
signal to
indicate that the data is incorrect. The
local_rdata_error
signal follows the same
timing as the
local_rdata_valid
signal.
Enabling auto-correction allows the ECC logic to hold off all controller pending
activities until the correction is completed. You can choose to disable auto-correction
and schedule the correction manually when the controller is idle to ensure better
system efficiency. To manually correct ECC errors, do the following:
1. When an interrupt occurs, read the
SBE_ERROR
register. When a single-bit error
occurs, the
SBE_ERROR
register is equal to one.
2. Read out the
ERR_ADDR
register.
3. Correct the single-bit error by doing one of the following:
■ Issue a dummy write to the memory address stored in the
ERR_ADDR
register. A
dummy write is a write request with the
local_be
signal zero, that triggers a
partial write which is effectively a read-modify-write event. The partial write
corrects the data at that address and writes it back.
or
■ Enable the
ENABLE_AUTO_CORR
register using the CSR interface and issue a read
request to the memory address stored in the
ERR_ADDR
register. The read
request triggers auto-error correction to the memory address stored in the
ERR_ADDR
register.
Partial Writes
The ECC logic supports partial writes. Along with the address, data, and burst
signals, the Avalon-MM interface also supports a signal vector,
local_be
, that is
responsible for byte-enable. Every bit of this signal vector represents a byte on the
data-bus. Thus, a logic low on any of these bits instructs the controller not to write to
that particular byte, resulting in a partial write. The ECC code is calculated on all
bytes of the data-bus. If any bytes are changed, the ECC code must be recalculated
and the new code must be written back to the memory.
For partial writes, the ECC logic performs the following steps:
- User Guide 1
- Contents 3
- Chapter 8. Latency 5
- Chapter 9. Timing Diagrams 5
- 1. About This IP 7
- Release Information 8
- Device Family Support 8
- 1–4 Chapter 1: About This IP 10
- Features 10
- ALTMEMPHY Megafunction 11
- Note to Table 1–4: 12
- Note to Table 1–5: 12
- High-Performance Controller 13
- System Requirements 14
- Installation and Licensing 14
- Free Evaluation 15
- 1–10 Chapter 1: About This IP 16
- 2. Getting Started 17
- Specifying Parameters 18
- SOPC Builder Flow 19
- Generated Files 22
- 3. Parameter Settings 29
- Memory Settings 30
- ALTMEMPHY Parameter Settings 31
- Note to Table 3–3: 34
- Note to Table 3–5: 38
- PHY Settings 39
- Board Settings 41
- Controller Settings 42
- 4. Compiling and Simulating 47
- Compiling the Design 48
- Simulating the Design 50
- Calibration 55
- DDR3 SDRAM Without Leveling 55
- Step 6: Postamble 57
- Step 7: Prepare for User Mode 57
- DDR3 SDRAM With Leveling 59
- Step 2: Write Leveling 62
- Address and Command Datapath 63
- ° ), or the inverted 64
- Clock and Reset Management 65
- Clock Management 65
- Note to Table 5–1: 67
- Reset Management 69
- Read Datapath 70
- Write Datapath 74
- ALTMEMPHY Signals 75
- Notes to Table 5–3: 77
- Note to Table 5–3: 79
- Notes to Table 5–5: 82
- PHY-to-Controller Interfaces 83
- Notes to Figure 5–17: 86
- Notes to Figure 5–18: 87
- Notes to Figure 5–19: 88
- Notes to Figure 5–20: 89
- Preliminary Steps 90
- Design Considerations 90
- Clocks and Resets 90
- Using a Custom Controller 91
- 6. Functional Description— 95
- Command FIFO Buffer 96
- PHY Interface Logic 98
- Control Logic 99
- Figure 6–3. ECC Block Diagram 100
- Block Description 101
- Interrupts 102
- Partial Writes 102
- Partial Bursts 103
- ECC Latency 103
- ECC Registers 104
- ECC Register Bits 106
- Example Top-Level File 108
- Example Driver 109
- Top-level Signals Description 110
- or vhd file 111
- Note to Table 6–14: 114
- 7. Functional Description— 117
- Write Data FIFO Buffer 120
- Command Queue 120
- Bank Management Logic 120
- Timer Logic 121
- Command-Issuing State Machine 121
- ODT Generation Logic 122
- User-Refresh Commands 122
- Multi-Cast Write 122
- Low-Power Mode Logic 123
- Error Correction Coding (ECC) 123
- Notes to Table 7–7: 133
- Register Maps Description 134
- ALTMEMPHY Register Map 135
- Controller Register Map 137
- 8. Latency 143
- 8–2 Chapter 8: Latency 144
- Chapter 8: Latency 8–3 145
- 8–4 Chapter 8: Latency 146
- 9. Timing Diagrams 147
- Auto-Precharge 148
- [1] [2] [3] 148
- User Refresh 149
- Initialization Timing 156
- Calibration Timing 158
- AABBCCDD AABBCCDD AABBCCDD 162
- EEFF0011 EEFF0011 EEFF0011 162
- [1] [3] [4][2] 166
- Half-Rate Read With Gaps 168
- Half-Rate Write With Gaps 169
- [2][1] [5] [4] [6][3] 170
- [12][6][7][10] [11] 172
- Additional Information 175
- Typographic Conventions 176
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