Altera Nios Development Board Manuel d'utilisateur Page 9
- Page / 56
- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Altera Corporation 1–1
July 2005
Introduction
Features
Overview
The Nios development board, Stratix II Edition, provides a hardware
platform for developing embedded systems based on Altera Stratix II
devices. The Nios development board, Stratix II Edition provides the
following features:
■ A Stratix II FPGA with more than 13,500 adaptive logic modules
(ALM) and 1.3 million bits of on-chip memory
■ 16 Mbytes of flash memory
■ 1Mbyte of static RAM
■ 16 Mbytes of SDRAM
■ On board logic for configuring the Stratix II device from flash
memory
■ On-board Ethernet MAC/PHY device
■ Two 5V-tolerant expansion/prototype headers each with access to 41
Stratix II user I/O pins
■ CompactFlash
TM
connector for Type I CompactFlash cards
■ Mictor connector for hardware and software debug
■ Two RS-232 DB9 serial ports
■ Four push-button switches connected to Stratix II user I/O pins
■ Eight LEDs connected to Stratix II user I/O pins
■ Dual 7-segment LED display
■ JTAG connectors to Altera
®
devices via Altera download cables
■ 50 MHz oscillator and zero-skew clock distribution circuitry
■ Power-on reset circuitry
General
Description
The Nios development board comes pre-programmed with a Nios II
processor reference design. Hardware designers can use the reference
design as an example of how to use the features of the Nios development
board. Software designers can use the pre-programmed Nios II processor
design on the board to begin prototyping software immediately.
This document describes the hardware features of the Nios development
board, including detailed pin-out information, to enable designers to
create custom FPGA designs that interface with all components on the
board.
f Refer to the Nios II Development Kit, Getting Started User Guide for
instructions on setting up the Nios development board and installing
Nios II development tools.
- Nios Development Board 1
- MNL-N832T4-1.2 2
- Contents 3
- Shared Bus Table 1 4
- About this Manual 5
- How to Contact 6
- Typographic 7
- Conventions 7
- July 2005 8
- Typographic Conventions 8
- Introduction 9
- 1–2 Altera Corporation 10
- General Description 10
- Factory 11
- Programmed 11
- Reference 11
- 1–4 Altera Corporation 12
- Board Components 13
- Stratix II Device 15
- Push-Button 17
- Switches (SW0 17
- Individual LEDs 17
- (D0 - D7) 17
- Seven-Segment 18
- LEDs (U8 & U9) 18
- SRAM Memory 18
- (U35 & U36) 18
- Flash Memory 19
- SDRAM Memory 20
- Ethernet 22
- MAC/PHY (U4) 22
- Serial Port 22
- Connectors (J19 22
- & J27) 22
- Expansion 23
- Prototype 23
- Connectors 23
- (PROTO1 & 23
- Altera Corporation 2–17 25
- Note to Figure 2–8 25
- 2–18 Altera Corporation 26
- Altera Corporation 2–19 27
- Notes to Figure 2–10 27
- CompactFlash 28
- Connector 28
- Connector (J25) 31
- 2–24 Altera Corporation 32
- Mictor Connector (J25) 32
- Configuration 33
- Controller 33
- Device (U3) 33
- Factory & User 34
- Configurations 34
- Flash Memory Partitions 35
- User Configuration 36
- Factory Configuration 36
- Persistent Data 36
- Configuration-Status LEDs 37
- SW8 – CPU Reset 38
- SW9 – Factory Config 38
- SW10 – Reset, Config 38
- Connectors (J24 39
- & J5) 39
- 2–32 Altera Corporation 40
- ° compared to J24 41
- Clock Circuitry 42
- Power-Supply 43
- Circuitry 43
- 2–36 Altera Corporation 44
- Power-Supply Circuitry 44
- Appendix A. Shared Bus Table 45
- Shared Data 46
- WE_n.ACC 47
- A–4 Altera Corporation 48
- July 2005 48
- Description 48
- Appendix B. Restoring the 49
- B–2 Altera Corporation 50
- Appendix C. Connecting to the 51
- Board via Ethernet 51
- Connecting the 52
- LCD Screen 52
- Obtaining an IP 52
- LAN Connection 53
- Point–to–Point Connections 54
- Browsing to Your 55
- C–6 Altera Corporation 56
- Browsing to Your Board 56
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