Altera Nios Development Board Manuel d'utilisateur Page 45
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Noté. / 5. Basé sur avis des utilisateurs
Altera Corporation A–1
July 2005
Appendix A. Shared Bus Table
Description
On the Nios development board, Stratix II edition, the flash memory,
SRAM and Ethernet MAC/PHY devices share address and control lines.
These shared lines are referred to as the Shared Bus. Using SOPC Builder,
designers can interface a Nios II processor system to any device
connected to the off-chip Shared Bus. Tab le A –9 o n pag e A–1 lists all
connections between the devices connected to the Shared Bus.
Table A–9. Shared Bus Table (Part 1 of 3)
NET Name
NET
Description
PLD (U60) Flash (U5) SRAM (U35) SRAM (U36) Ethernet (U4)
Pin
Name
Pin #
Pin
Name
Pin #
Pin
Name
Pin #
Pin
Name
Pin #
Pin
Name
Pin #
FSE_A0
Shared
Address
IO T2 D15/A-1 51
FSE_A1
IO T3 A0 31 A1 78
FSE_A2
IOU1 A1 26A01A01 A2 79
FSE_A3
IO U2 A2 25 A1 2 A1 2 A3 80
FSE_A4
IO V1 A3 24 A2 3 A2 3 A4 81
FSE_A5
IO V2 A4 23 A3 4 A3 4 A5 82
FSE_A6
IOW1 A5 22A45A45 A6 83
FSE_A7
IO W2 A6 21 A5 18 A5 18 A7 84
FSE_A8
IO Y1 A7 20 A6 19 A6 19 A8 85
FSE_A9
IO Y2 A8 10 A7 20 A7 20 A9 86
FSE_A10
IO AA1 A9 9 A8 21 A8 21 A10 87
FSE_A11
IO AA2 A10 8 A9 22 A9 22 A11 88
FSE_A12
IO AB1 A11 7 A10 23 A10 23 A12 89
FSE_A13
IO AB2 A12 6 A11 24 A11 24 A13 90
FSE_A14
IO W3 A13 5 A12 25 A12 25 A14 91
FSE_A15
IO W4 A14 4 A13 26 A13 26 A15 92
FSE_A16
IO Y3 A15 3 A14 27 A14 27
FSE_A17
IO Y4 A16 54 A15 42 A15 42
FSE_A18
IO AA3 A17 19 A16 43 A16 43
FSE_A19
IO AA4 A18 18 A17 44 A17 44
FSE_A20
IO AB3 A19 11
FSE_A21
IO AB4 A20 12
FSE_A22
IO AC2 A21 15
FSE_A23
IO AC3 A22 2
FSE_A24
IO P5
NC.A23
(1)
1
- Nios Development Board 1
- MNL-N832T4-1.2 2
- Contents 3
- Shared Bus Table 1 4
- About this Manual 5
- How to Contact 6
- Typographic 7
- Conventions 7
- July 2005 8
- Typographic Conventions 8
- Introduction 9
- 1–2 Altera Corporation 10
- General Description 10
- Factory 11
- Programmed 11
- Reference 11
- 1–4 Altera Corporation 12
- Board Components 13
- Stratix II Device 15
- Push-Button 17
- Switches (SW0 17
- Individual LEDs 17
- (D0 - D7) 17
- Seven-Segment 18
- LEDs (U8 & U9) 18
- SRAM Memory 18
- (U35 & U36) 18
- Flash Memory 19
- SDRAM Memory 20
- Ethernet 22
- MAC/PHY (U4) 22
- Serial Port 22
- Connectors (J19 22
- & J27) 22
- Expansion 23
- Prototype 23
- Connectors 23
- (PROTO1 & 23
- Altera Corporation 2–17 25
- Note to Figure 2–8 25
- 2–18 Altera Corporation 26
- Altera Corporation 2–19 27
- Notes to Figure 2–10 27
- CompactFlash 28
- Connector 28
- Connector (J25) 31
- 2–24 Altera Corporation 32
- Mictor Connector (J25) 32
- Configuration 33
- Controller 33
- Device (U3) 33
- Factory & User 34
- Configurations 34
- Flash Memory Partitions 35
- User Configuration 36
- Factory Configuration 36
- Persistent Data 36
- Configuration-Status LEDs 37
- SW8 – CPU Reset 38
- SW9 – Factory Config 38
- SW10 – Reset, Config 38
- Connectors (J24 39
- & J5) 39
- 2–32 Altera Corporation 40
- ° compared to J24 41
- Clock Circuitry 42
- Power-Supply 43
- Circuitry 43
- 2–36 Altera Corporation 44
- Power-Supply Circuitry 44
- Appendix A. Shared Bus Table 45
- Shared Data 46
- WE_n.ACC 47
- A–4 Altera Corporation 48
- July 2005 48
- Description 48
- Appendix B. Restoring the 49
- B–2 Altera Corporation 50
- Appendix C. Connecting to the 51
- Board via Ethernet 51
- Connecting the 52
- LCD Screen 52
- Obtaining an IP 52
- LAN Connection 53
- Point–to–Point Connections 54
- Browsing to Your 55
- C–6 Altera Corporation 56
- Browsing to Your Board 56
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