Altera Nios Development Board Manuel d'utilisateur Page 16
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
2–8 Altera Corporation
Nios Development Board Reference Manual, Stratix II Edition July 2005
Stratix II Device (U60)
The development board provides two separate methods for configuring
the Stratix II device:
1. Using the Quartus II software running on a host computer, a
designer configures the device directly via an Altera
®
download
cable connected to the Stratix II JTAG header (J24).
2. When power is applied to the board, a configuration controller
device (U3) attempts to configure the Stratix II device with
hardware configuration data stored in flash memory. For more
information on the configuration controller, see “Configuration
Controller Device (U3)” on page 2–25.
f For Stratix II-related documentation including Stratix II pinout data refer
to the Altera Stratix II literature page at www.altera.com/ literature/lit-
stx2.html.
Early shipments of the board had a heat sink mounted on the Stratix II
FPGA. Boards shipped later than May 2005 do not include the heat sink,
because thermal management is unnecessary for the majority of FPGA
designs for this board. A heat sink maintains the FPGA within its
specified thermal operating range, independent of the resource
utilization, clock frequency, and operating conditions of the FPGA. The
heat sink used on early shipments of the board is produced by Intricast
Inc., part number CS1995V01. See www.intricast.com for details.
f Refer to Altera's AN185: Thermal Management Using Heat Sinks for
information on using heat sinks with Altera devices.
18-bit x 18-bit multipliers 64 144
Enhanced PLLS 2 4
Fast PLLs 4 8
User I/O pins 500 492
Table 2–2. Stratix II Device Features (Part 2 of 2)
Feature EP2S30 EP2S60
- Nios Development Board 1
- MNL-N832T4-1.2 2
- Contents 3
- Shared Bus Table 1 4
- About this Manual 5
- How to Contact 6
- Typographic 7
- Conventions 7
- July 2005 8
- Typographic Conventions 8
- Introduction 9
- 1–2 Altera Corporation 10
- General Description 10
- Factory 11
- Programmed 11
- Reference 11
- 1–4 Altera Corporation 12
- Board Components 13
- Stratix II Device 15
- Push-Button 17
- Switches (SW0 17
- Individual LEDs 17
- (D0 - D7) 17
- Seven-Segment 18
- LEDs (U8 & U9) 18
- SRAM Memory 18
- (U35 & U36) 18
- Flash Memory 19
- SDRAM Memory 20
- Ethernet 22
- MAC/PHY (U4) 22
- Serial Port 22
- Connectors (J19 22
- & J27) 22
- Expansion 23
- Prototype 23
- Connectors 23
- (PROTO1 & 23
- Altera Corporation 2–17 25
- Note to Figure 2–8 25
- 2–18 Altera Corporation 26
- Altera Corporation 2–19 27
- Notes to Figure 2–10 27
- CompactFlash 28
- Connector 28
- Connector (J25) 31
- 2–24 Altera Corporation 32
- Mictor Connector (J25) 32
- Configuration 33
- Controller 33
- Device (U3) 33
- Factory & User 34
- Configurations 34
- Flash Memory Partitions 35
- User Configuration 36
- Factory Configuration 36
- Persistent Data 36
- Configuration-Status LEDs 37
- SW8 – CPU Reset 38
- SW9 – Factory Config 38
- SW10 – Reset, Config 38
- Connectors (J24 39
- & J5) 39
- 2–32 Altera Corporation 40
- ° compared to J24 41
- Clock Circuitry 42
- Power-Supply 43
- Circuitry 43
- 2–36 Altera Corporation 44
- Power-Supply Circuitry 44
- Appendix A. Shared Bus Table 45
- Shared Data 46
- WE_n.ACC 47
- A–4 Altera Corporation 48
- July 2005 48
- Description 48
- Appendix B. Restoring the 49
- B–2 Altera Corporation 50
- Appendix C. Connecting to the 51
- Board via Ethernet 51
- Connecting the 52
- LCD Screen 52
- Obtaining an IP 52
- LAN Connection 53
- Point–to–Point Connections 54
- Browsing to Your 55
- C–6 Altera Corporation 56
- Browsing to Your Board 56
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