Altera Nios Development Board Manuel d'utilisateur Page 15
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Altera Corporation 2–7
July 2005 Nios Development Board Reference Manual, Stratix II Edition
Board Components
The sections that follow describe each component in detail.
Stratix II Device
(U60)
U60 is a Stratix II FPGA in a 672-pin FineLine BGA® package. Early
shipments of the Nios Development Board, Stratix II Edition included an
EP2S60F672C5 device. Some early boards used engineering sample parts,
indicated by “ES” after the part number. Later shipments of the board use
an EP2S30F672C5 device. Table 2–2 lists the device features.
SW8 CPU Reset button Push-button switch to reboot the Nios II processor configured
in the FPGA
SW9 Factory Config
button
Push-button switch to reconfigure the FPGA with the factory-
programmed reference design
SW10 Reset, Config Push-button switch to reset the board
LED0 – LED3 Configuration
status LEDs
LEDs that display the current configuration status of the
FPGA
Clock Circuitry
Y2 Oscillator 50 MHz clock signal driven to FPGA
J4 External clock
input
Connector to FPGA clock pin
Power Supply
J26 DC power jack 17 V DC unregulated power source
D34 Bridge rectifier Power rectifier allows for center-negative or center-positive
power supplies
Table 2–1. Nios Development Board, Stratix Edition Components & Interfaces (Part 2 of 2)
Board Designation Name Description
Table 2–2. Stratix II Device Features (Part 1 of 2)
Feature EP2S30 EP2S60
ALMs 13,552 24,176
Adaptive look-up tables (ALUTs) 27,104 48,352
Equivalent LEs 33,880 60,440
M512 RAM blocks 202 329
M4K RAM blocks 144 255
M-RAM blocks 1 2
Total RAM bits 1,369,728 2,544,192
DSP blocks 16 36
- Nios Development Board 1
- MNL-N832T4-1.2 2
- Contents 3
- Shared Bus Table 1 4
- About this Manual 5
- How to Contact 6
- Typographic 7
- Conventions 7
- July 2005 8
- Typographic Conventions 8
- Introduction 9
- 1–2 Altera Corporation 10
- General Description 10
- Factory 11
- Programmed 11
- Reference 11
- 1–4 Altera Corporation 12
- Board Components 13
- Stratix II Device 15
- Push-Button 17
- Switches (SW0 17
- Individual LEDs 17
- (D0 - D7) 17
- Seven-Segment 18
- LEDs (U8 & U9) 18
- SRAM Memory 18
- (U35 & U36) 18
- Flash Memory 19
- SDRAM Memory 20
- Ethernet 22
- MAC/PHY (U4) 22
- Serial Port 22
- Connectors (J19 22
- & J27) 22
- Expansion 23
- Prototype 23
- Connectors 23
- (PROTO1 & 23
- Altera Corporation 2–17 25
- Note to Figure 2–8 25
- 2–18 Altera Corporation 26
- Altera Corporation 2–19 27
- Notes to Figure 2–10 27
- CompactFlash 28
- Connector 28
- Connector (J25) 31
- 2–24 Altera Corporation 32
- Mictor Connector (J25) 32
- Configuration 33
- Controller 33
- Device (U3) 33
- Factory & User 34
- Configurations 34
- Flash Memory Partitions 35
- User Configuration 36
- Factory Configuration 36
- Persistent Data 36
- Configuration-Status LEDs 37
- SW8 – CPU Reset 38
- SW9 – Factory Config 38
- SW10 – Reset, Config 38
- Connectors (J24 39
- & J5) 39
- 2–32 Altera Corporation 40
- ° compared to J24 41
- Clock Circuitry 42
- Power-Supply 43
- Circuitry 43
- 2–36 Altera Corporation 44
- Power-Supply Circuitry 44
- Appendix A. Shared Bus Table 45
- Shared Data 46
- WE_n.ACC 47
- A–4 Altera Corporation 48
- July 2005 48
- Description 48
- Appendix B. Restoring the 49
- B–2 Altera Corporation 50
- Appendix C. Connecting to the 51
- Board via Ethernet 51
- Connecting the 52
- LCD Screen 52
- Obtaining an IP 52
- LAN Connection 53
- Point–to–Point Connections 54
- Browsing to Your 55
- C–6 Altera Corporation 56
- Browsing to Your Board 56
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