Altera MAX 10 Clocking and PLL Manuel d'utilisateur Page 17
- Page / 86
- Table des matières
- MARQUE LIVRES
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Altera Corporation 3
- Clock Networks Overview 5
- Internal Oscillator Overview 5
- PLLs Overview 5
- • PLL cascading 6
- • Reference clock switchover 6
- Features 7
- Clock Resources 8
- Global Clock Network Sources 8
- Pin GCLK 9
- Global Clock Control Block 10
- Input Description 11
- Related Information 12
- Clock Enable Signals 13
- PLL Architecture 14
- UG-M10CLKPLL 15
- 2015.05.04 15
- PLL Features 16
- PLL Locations 16
- Clock Pin to PLL Connections 18
- PLL Control Signals 19
- Clock Feedback Modes 20
- Source Synchronous Mode 21
- No Compensation Mode 21
- Normal Mode 22
- PLL External Clock Output 23
- ADC Clock Input from PLL 25
- Spread-Spectrum Clocking 25
- PLL Programmable Parameters 25
- Programmable Phase Shift 26
- Clock Switchover 28
- Manual Clock Switchover 31
- PLL Cascading 32
- PLL Reconfiguration 32
- Considerations 35
- PLLs Design Considerations 36
- Guideline: PLL Cascading 37
- Guideline: Clock Switchover 37
- ALTCLKCTRL IP Core 39
- Search for installed IP cores 40
- ALTPLL IP Core 43
- Block Name 50
- Number of Bits 50
- Counter Control Bit Total 50
- 3. Ignore this directory 55
- ALTPLL_RECONFIG IP Core 56
- Internal Oscillator IP Core 59
- ALTCLKCTRL IP Core References 64
- ALTCLKCTRL Ports and Signals 65
- ALTPLL IP Core References 67
- Parameter Value Description 68
- ALTPLL Ports and Signals 72
- Port Name 73
- Condition Description 73
- ALTPLL_RECONFIG Parameters 77
- Parameter Value Decription 85
- Date Version Changes 86
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