Altera Interlaken MegaCore Function Manuel d'utilisateur télécharger pdf (Page 84)

C–4 Appendix C: Closing Timing on 10- and 20-lane Designs

Interlaken MegaCore Function June 2012 Altera Corporation

User Guide

set_instance_assignment -name GLOBAL_SIGNAL OFF \

-from *transmit_pma0*clockout -to *tx_launch[*]

c. Make PCLK assignments on remaining failing

tx_launch

registers. Depending

on your paths, you might add a line similar to the following example

assignment to your .qsf file:

set_instance_assignment -name GLOBAL_SIGNAL “PERIPHERY CLOCK”\

-from *transmit_pma0*clockout -to *tx_prelaunch[*]

d. Check the remaining failing paths, and force manual placement if needed.

e. Repeat as needed.

f For more information about LogicLock regions, refer to the Quartus II Incremental

Compilation for Hierarchical and Team-Based Design chapter in volume 1 of the Quartus II

Handbook.

f For more information about the TimeQuest Timing Analyzer, refer to the Quartus II

Help and The Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the

Quartus II Handbook.

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Altera Interlaken MegaCore Function Manuel d'utilisateur Page 84